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This patch writes a mapping structure for converting CodeView Arm64 register numbers to LLDB Arm64 regnums. This fixes various symbols and variable location test failures on AArch64/Windows. https://reviews.llvm.org/D128221 Files: lldb/source/Plugins/SymbolFile/NativePDB/CodeViewRegisterMapping.cpp
Index: lldb/source/Plugins/SymbolFile/NativePDB/CodeViewRegisterMapping.cpp =================================================================== --- lldb/source/Plugins/SymbolFile/NativePDB/CodeViewRegisterMapping.cpp +++ lldb/source/Plugins/SymbolFile/NativePDB/CodeViewRegisterMapping.cpp @@ -10,10 +10,196 @@ #include "lldb/lldb-defines.h" +#include "Plugins/Process/Utility/lldb-arm64-register-enums.h" #include "Plugins/Process/Utility/lldb-x86-register-enums.h" using namespace lldb_private; +static const uint32_t g_code_view_to_lldb_registers_arm64[] = { + LLDB_INVALID_REGNUM, // NONE + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + gpr_w0_arm64, // ARM64_W0, 10) + gpr_w1_arm64, // ARM64_W1, 11) + gpr_w2_arm64, // ARM64_W2, 12) + gpr_w3_arm64, // ARM64_W3, 13) + gpr_w4_arm64, // ARM64_W4, 14) + gpr_w5_arm64, // ARM64_W5, 15) + gpr_w6_arm64, // ARM64_W6, 16) + gpr_w7_arm64, // ARM64_W7, 17) + gpr_w8_arm64, // ARM64_W8, 18) + gpr_w9_arm64, // ARM64_W9, 19) + gpr_w10_arm64, // ARM64_W10, 20) + gpr_w11_arm64, // ARM64_W11, 21) + gpr_w12_arm64, // ARM64_W12, 22) + gpr_w13_arm64, // ARM64_W13, 23) + gpr_w14_arm64, // ARM64_W14, 24) + gpr_w15_arm64, // ARM64_W15, 25) + gpr_w16_arm64, // ARM64_W16, 26) + gpr_w17_arm64, // ARM64_W17, 27) + gpr_w18_arm64, // ARM64_W18, 28) + gpr_w19_arm64, // ARM64_W19, 29) + gpr_w20_arm64, // ARM64_W20, 30) + gpr_w21_arm64, // ARM64_W21, 31) + gpr_w22_arm64, // ARM64_W22, 32) + gpr_w23_arm64, // ARM64_W23, 33) + gpr_w24_arm64, // ARM64_W24, 34) + gpr_w25_arm64, // ARM64_W25, 35) + gpr_w26_arm64, // ARM64_W26, 36) + gpr_w27_arm64, // ARM64_W27, 37) + gpr_w28_arm64, // ARM64_W28, 38) + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + gpr_x0_arm64, // ARM64_X0, 50) + gpr_x1_arm64, // ARM64_X1, 51) + gpr_x2_arm64, // ARM64_X2, 52) + gpr_x3_arm64, // ARM64_X3, 53) + gpr_x4_arm64, // ARM64_X4, 54) + gpr_x5_arm64, // ARM64_X5, 55) + gpr_x6_arm64, // ARM64_X6, 56) + gpr_x7_arm64, // ARM64_X7, 57) + gpr_x8_arm64, // ARM64_X8, 58) + gpr_x9_arm64, // ARM64_X9, 59) + gpr_x10_arm64, // ARM64_X10, 60) + gpr_x11_arm64, // ARM64_X11, 61) + gpr_x12_arm64, // ARM64_X12, 62) + gpr_x13_arm64, // ARM64_X13, 63) + gpr_x14_arm64, // ARM64_X14, 64) + gpr_x15_arm64, // ARM64_X15, 65) + gpr_x16_arm64, // ARM64_X16, 66) + gpr_x17_arm64, // ARM64_X17, 67) + gpr_x18_arm64, // ARM64_X18, 68) + gpr_x19_arm64, // ARM64_X19, 69) + gpr_x20_arm64, // ARM64_X20, 70) + gpr_x21_arm64, // ARM64_X21, 71) + gpr_x22_arm64, // ARM64_X22, 72) + gpr_x23_arm64, // ARM64_X23, 73) + gpr_x24_arm64, // ARM64_X24, 74) + gpr_x25_arm64, // ARM64_X25, 75) + gpr_x26_arm64, // ARM64_X26, 76) + gpr_x27_arm64, // ARM64_X27, 77) + gpr_x28_arm64, // ARM64_X28, 78) + gpr_fp_arm64, // ARM64_FP, 79) + gpr_lr_arm64, // ARM64_LR, 80) + gpr_sp_arm64, // ARM64_SP, 81) + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + gpr_cpsr_arm64, // ARM64_NZCV, 90) + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s0_arm64, // (ARM64_S0, 100) + fpu_s1_arm64, // (ARM64_S1, 101) + fpu_s2_arm64, // (ARM64_S2, 102) + fpu_s3_arm64, // (ARM64_S3, 103) + fpu_s4_arm64, // (ARM64_S4, 104) + fpu_s5_arm64, // (ARM64_S5, 105) + fpu_s6_arm64, // (ARM64_S6, 106) + fpu_s7_arm64, // (ARM64_S7, 107) + fpu_s8_arm64, // (ARM64_S8, 108) + fpu_s9_arm64, // (ARM64_S9, 109) + fpu_s10_arm64, // (ARM64_S10, 110) + fpu_s11_arm64, // (ARM64_S11, 111) + fpu_s12_arm64, // (ARM64_S12, 112) + fpu_s13_arm64, // (ARM64_S13, 113) + fpu_s14_arm64, // (ARM64_S14, 114) + fpu_s15_arm64, // (ARM64_S15, 115) + fpu_s16_arm64, // (ARM64_S16, 116) + fpu_s17_arm64, // (ARM64_S17, 117) + fpu_s18_arm64, // (ARM64_S18, 118) + fpu_s19_arm64, // (ARM64_S19, 119) + fpu_s20_arm64, // (ARM64_S20, 120) + fpu_s21_arm64, // (ARM64_S21, 121) + fpu_s22_arm64, // (ARM64_S22, 122) + fpu_s23_arm64, // (ARM64_S23, 123) + fpu_s24_arm64, // (ARM64_S24, 124) + fpu_s25_arm64, // (ARM64_S25, 125) + fpu_s26_arm64, // (ARM64_S26, 126) + fpu_s27_arm64, // (ARM64_S27, 127) + fpu_s28_arm64, // (ARM64_S28, 128) + fpu_s29_arm64, // (ARM64_S29, 129) + fpu_s30_arm64, // (ARM64_S30, 130) + fpu_s31_arm64, // (ARM64_S31, 131) + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d0_arm64, // (ARM64_D0, 140) + fpu_d1_arm64, // (ARM64_D1, 141) + fpu_d2_arm64, // (ARM64_D2, 142) + fpu_d3_arm64, // (ARM64_D3, 143) + fpu_d4_arm64, // (ARM64_D4, 144) + fpu_d5_arm64, // (ARM64_D5, 145) + fpu_d6_arm64, // (ARM64_D6, 146) + fpu_d7_arm64, // (ARM64_D7, 147) + fpu_d8_arm64, // (ARM64_D8, 148) + fpu_d9_arm64, // (ARM64_D9, 149) + fpu_d10_arm64, // (ARM64_D10, 150) + fpu_d11_arm64, // (ARM64_D11, 151) + fpu_d12_arm64, // (ARM64_D12, 152) + fpu_d13_arm64, // (ARM64_D13, 153) + fpu_d14_arm64, // (ARM64_D14, 154) + fpu_d15_arm64, // (ARM64_D15, 155) + fpu_d16_arm64, // (ARM64_D16, 156) + fpu_d17_arm64, // (ARM64_D17, 157) + fpu_d18_arm64, // (ARM64_D18, 158) + fpu_d19_arm64, // (ARM64_D19, 159) + fpu_d20_arm64, // (ARM64_D20, 160) + fpu_d21_arm64, // (ARM64_D21, 161) + fpu_d22_arm64, // (ARM64_D22, 162) + fpu_d23_arm64, // (ARM64_D23, 163) + fpu_d24_arm64, // (ARM64_D24, 164) + fpu_d25_arm64, // (ARM64_D25, 165) + fpu_d26_arm64, // (ARM64_D26, 166) + fpu_d27_arm64, // (ARM64_D27, 167) + fpu_d28_arm64, // (ARM64_D28, 168) + fpu_d29_arm64, // (ARM64_D29, 169) + fpu_d30_arm64, // (ARM64_D30, 170) + fpu_d31_arm64, // (ARM64_D31, 171) + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_v0_arm64, // (ARM64_Q0, 180) + fpu_v1_arm64, // (ARM64_Q1, 181) + fpu_v2_arm64, // (ARM64_Q2, 182) + fpu_v3_arm64, // (ARM64_Q3, 183) + fpu_v4_arm64, // (ARM64_Q4, 184) + fpu_v5_arm64, // (ARM64_Q5, 185) + fpu_v6_arm64, // (ARM64_Q6, 186) + fpu_v7_arm64, // (ARM64_Q7, 187) + fpu_v8_arm64, // (ARM64_Q8, 188) + fpu_v9_arm64, // (ARM64_Q9, 189) + fpu_v10_arm64, // (ARM64_Q10, 190) + fpu_v11_arm64, // (ARM64_Q11, 191) + fpu_v12_arm64, // (ARM64_Q12, 192) + fpu_v13_arm64, // (ARM64_Q13, 193) + fpu_v14_arm64, // (ARM64_Q14, 194) + fpu_v15_arm64, // (ARM64_Q15, 195) + fpu_v16_arm64, // (ARM64_Q16, 196) + fpu_v17_arm64, // (ARM64_Q17, 197) + fpu_v18_arm64, // (ARM64_Q18, 198) + fpu_v19_arm64, // (ARM64_Q19, 199) + fpu_v20_arm64, // (ARM64_Q20, 200) + fpu_v21_arm64, // (ARM64_Q21, 201) + fpu_v22_arm64, // (ARM64_Q22, 202) + fpu_v23_arm64, // (ARM64_Q23, 203) + fpu_v24_arm64, // (ARM64_Q24, 204) + fpu_v25_arm64, // (ARM64_Q25, 205) + fpu_v26_arm64, // (ARM64_Q26, 206) + fpu_v27_arm64, // (ARM64_Q27, 207) + fpu_v28_arm64, // (ARM64_Q28, 208) + fpu_v29_arm64, // (ARM64_Q29, 209) + fpu_v30_arm64, // (ARM64_Q30, 210) + fpu_v31_arm64, // (ARM64_Q31, 211) + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_fpsr_arm64 // ARM64_FPSR, 220) +}; + static const uint32_t g_code_view_to_lldb_registers_x86[] = { LLDB_INVALID_REGNUM, // NONE lldb_al_i386, // AL @@ -424,6 +610,14 @@ uint32_t lldb_private::npdb::GetLLDBRegisterNumber( llvm::Triple::ArchType arch_type, llvm::codeview::RegisterId register_id) { switch (arch_type) { + case llvm::Triple::aarch64: + if (static_cast<uint16_t>(register_id) < + sizeof(g_code_view_to_lldb_registers_arm64) / + sizeof(g_code_view_to_lldb_registers_arm64[0])) + return g_code_view_to_lldb_registers_arm64[static_cast<uint16_t>( + register_id)]; + + return LLDB_INVALID_REGNUM; case llvm::Triple::x86: if (static_cast<uint16_t>(register_id) < sizeof(g_code_view_to_lldb_registers_x86) /
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