Emmmer updated this revision to Diff 443482.
Emmmer added a comment.
This patch change:
- Add the recognition of architecture riscv64 in `HostInfoBase.cpp`
- Add the recognition of architecture riscv64 and riscv32 in
`ObjectFilePECOFF.cpp`
- Add riscv's `ebreak` command to `Platform.cpp`
Now lldb can debug with simple executables on `qemu-system-riscv64` and be able
to attach to a `gdbserver`.
---
TODO: some unittest failed
bash
[ RUN ] TestBase.LaunchModePreservesEnvironment
/home/emmmer/git/llvm-project/lldb/unittests/tools/lldb-server/tests/LLGSTest.cpp:29:
Failure
Value of: llvm::detail::TakeExpected(ClientOr)
Expected: succeeded
Actual: failed (Unable to parse qRegisterInfo: generic)
[ FAILED ] TestBase.LaunchModePreservesEnvironment (662 ms)
[ RUN ] TestBase.vAttachRichError
Connection established.
Launched
'/home/emmmer/git/llvm-project/build-cross/tools/lldb/unittests/tools/lldb-server/./environment_check'
as process 1553...
lldb-server-local_build
Connection established.
Launched
'/home/emmmer/git/llvm-project/build-cross/tools/lldb/unittests/tools/lldb-server/./environment_check'
as process 1556...
lldb-server-local_build
/home/emmmer/git/llvm-project/lldb/unittests/tools/lldb-server/tests/LLGSTest.cpp:60:
Failure
Value of: llvm::detail::TakeExpected(ClientOr)
Expected: succeeded
Actual: failed (Unable to parse qRegisterInfo: generic)
[ FAILED ] TestBase.vAttachRichError (364 ms)
In riscv, the user-mode process cannot directly take the `pc` register but must
obtain the pc state through `auipc`, while the `pc` register is required to
exist in the test, so it failed.
---
bash
[ RUN ] DumpDataExtractorTest.Formats
/home/emmmer/git/llvm-project/lldb/unittests/Core/DumpDataExtractorTest.cpp:90:
Failure
Expected equality of these values:
expected
Which is: "{-nan -nan nan nan}"
result.GetString()
Which is: "{nan nan nan nan}"
[ FAILED ] DumpDataExtractorTest.Formats (25 ms)
The reason is currently unknown, and further verification is required
---
About buildbot: Unfortunately, as an individual developer, I may not have the
ability to maintain a 7*24-hour compile server or even a cluster, but I will do
my best to provide some test reports.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D128250/new/
https://reviews.llvm.org/D128250
Files:
lldb/source/Host/common/HostInfoBase.cpp
lldb/source/Plugins/ABI/RISCV64/CMakeLists.txt
lldb/source/Plugins/Architecture/CMakeLists.txt
lldb/source/Plugins/Architecture/RISCV32/ArchitectureRISCV32.cpp
lldb/source/Plugins/Architecture/RISCV32/ArchitectureRISCV32.h
lldb/source/Plugins/Architecture/RISCV32/CMakeLists.txt
lldb/source/Plugins/Architecture/RISCV64/ArchitectureRISCV64.cpp
lldb/source/Plugins/Architecture/RISCV64/ArchitectureRISCV64.h
lldb/source/Plugins/Architecture/RISCV64/CMakeLists.txt
lldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp
lldb/source/Plugins/Process/Linux/CMakeLists.txt
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
lldb/source/Plugins/Process/Utility/CMakeLists.txt
lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h
lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h
lldb/source/Target/Platform.cpp
lldb/source/Utility/ArchSpec.cpp
lldb/source/Utility/RISCV64_DWARF_Registers.h
Index: lldb/source/Utility/RISCV64_DWARF_Registers.h
===================================================================
--- /dev/null
+++ lldb/source/Utility/RISCV64_DWARF_Registers.h
@@ -0,0 +1,92 @@
+//===-- RISCV64_DWARF_Registers.h -------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_UTILITY_RISCV64_DWARF_REGISTERS_H
+#define LLDB_SOURCE_UTILITY_RISCV64_DWARF_REGISTERS_H
+
+#include "lldb/lldb-private.h"
+
+namespace riscv64_dwarf {
+
+enum {
+ x0 = 0,
+ x1,
+ x2,
+ x3,
+ x4,
+ x5,
+ x6,
+ x7,
+ x8,
+ x9,
+ x10,
+ x11,
+ x12,
+ x13,
+ x14,
+ x15,
+ x16,
+ x17,
+ x18,
+ x19,
+ x20,
+ x21,
+ x22,
+ x23,
+ x24,
+ x25,
+ x26,
+ x27,
+ x28,
+ x29,
+ x30,
+ x31,
+ ra = x1,
+ sp = x2,
+ fp = x8,
+
+ f0,
+ f1,
+ f2,
+ f3,
+ f4,
+ f5,
+ f6,
+ f7,
+ f8,
+ f9,
+ f10,
+ f11,
+ f12,
+ f13,
+ f14,
+ f15,
+ f16,
+ f17,
+ f18,
+ f19,
+ f20,
+ f21,
+ f22,
+ f23,
+ f24,
+ f25,
+ f26,
+ f27,
+ f28,
+ f29,
+ f30,
+ f31,
+
+ // Floating-Point Control and Status Register
+ fcsr,
+};
+
+} // namespace riscv64_dwarf
+
+#endif // LLDB_SOURCE_UTILITY_RISCV64_DWARF_REGISTERS_H
Index: lldb/source/Utility/ArchSpec.cpp
===================================================================
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -724,6 +724,8 @@
case llvm::Triple::systemz:
case llvm::Triple::xcore:
case llvm::Triple::arc:
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
return false;
}
}
@@ -1376,6 +1378,20 @@
}
break;
+ case ArchSpec::eCore_riscv32:
+ if (!enforce_exact_match) {
+ if (core2 == ArchSpec::eCore_riscv32)
+ return true;
+ }
+ break;
+
+ case ArchSpec::eCore_riscv64:
+ if (!enforce_exact_match) {
+ if (core2 == ArchSpec::eCore_riscv64)
+ return true;
+ }
+ break;
+
default:
break;
}
Index: lldb/source/Target/Platform.cpp
===================================================================
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1930,6 +1930,12 @@
trap_opcode_size = sizeof(g_i386_opcode);
} break;
+ case llvm::Triple::riscv64: {
+ static const uint8_t g_riscv64_opcode[] = {0x01, 0x00, 0x00, 0x73};
+ trap_opcode = g_riscv64_opcode;
+ trap_opcode_size = sizeof(g_riscv64_opcode);
+ } break;
+
default:
return 0;
}
Index: lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h
@@ -0,0 +1,262 @@
+//===-- RegisterInfos_riscv64.h ---------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifdef DECLARE_REGISTER_INFOS_RISCV64_STRUCT
+
+#include <stddef.h>
+
+#include "lldb/lldb-defines.h"
+#include "lldb/lldb-enumerations.h"
+#include "lldb/lldb-private.h"
+
+#include "Utility/RISCV64_DWARF_Registers.h"
+
+#ifndef GPR_OFFSET
+#error GPR_OFFSET must be defined before including this header file
+#endif
+
+#ifndef GPR_OFFSET_NAME
+#error GPR_OFFSET_NAME must be defined before including this header file
+#endif
+
+#ifndef FPR_OFFSET
+#error FPR_OFFSET must be defined before including this header file
+#endif
+
+#ifndef FPR_OFFSET_NAME
+#error FPR_OFFSET_NAME must be defined before including this header file
+#endif
+
+enum {
+ gpr_x0 = 0,
+ gpr_x1,
+ gpr_x2,
+ gpr_x3,
+ gpr_x4,
+ gpr_x5,
+ gpr_x6,
+ gpr_x7,
+ gpr_x8,
+ gpr_x9,
+ gpr_x10,
+ gpr_x11,
+ gpr_x12,
+ gpr_x13,
+ gpr_x14,
+ gpr_x15,
+ gpr_x16,
+ gpr_x17,
+ gpr_x18,
+ gpr_x19,
+ gpr_x20,
+ gpr_x21,
+ gpr_x22,
+ gpr_x23,
+ gpr_x24,
+ gpr_x25,
+ gpr_x26,
+ gpr_x27,
+ gpr_x28,
+ gpr_x29,
+ gpr_x30,
+ gpr_x31,
+ gpr_ra = gpr_x1,
+ gpr_sp = gpr_x2,
+ gpr_fp = gpr_x8,
+
+ fpr_f0,
+ fpr_f1,
+ fpr_f2,
+ fpr_f3,
+ fpr_f4,
+ fpr_f5,
+ fpr_f6,
+ fpr_f7,
+ fpr_f8,
+ fpr_f9,
+ fpr_f10,
+ fpr_f11,
+ fpr_f12,
+ fpr_f13,
+ fpr_f14,
+ fpr_f15,
+ fpr_f16,
+ fpr_f17,
+ fpr_f18,
+ fpr_f19,
+ fpr_f20,
+ fpr_f21,
+ fpr_f22,
+ fpr_f23,
+ fpr_f24,
+ fpr_f25,
+ fpr_f26,
+ fpr_f27,
+ fpr_f28,
+ fpr_f29,
+ fpr_f30,
+ fpr_f31,
+
+ fpr_d0,
+ fpr_d1,
+ fpr_d2,
+ fpr_d3,
+ fpr_d4,
+ fpr_d5,
+ fpr_d6,
+ fpr_d7,
+ fpr_d8,
+ fpr_d9,
+ fpr_d10,
+ fpr_d11,
+ fpr_d12,
+ fpr_d13,
+ fpr_d14,
+ fpr_d15,
+ fpr_d16,
+ fpr_d17,
+ fpr_d18,
+ fpr_d19,
+ fpr_d20,
+ fpr_d21,
+ fpr_d22,
+ fpr_d23,
+ fpr_d24,
+ fpr_d25,
+ fpr_d26,
+ fpr_d27,
+ fpr_d28,
+ fpr_d29,
+ fpr_d30,
+ fpr_d31,
+
+ fpr_fcsr,
+
+ k_num_registers
+};
+
+// Generates register kinds array with DWARF, EH frame and generic kind
+#define MISC_KIND(reg, type, generic_kind) \
+ { riscv64_dwarf::reg, generic_kind, LLDB_INVALID_REGNUM, type##_##reg }
+
+// Generates register kinds array for registers with only lldb kind
+#define LLDB_KIND(lldb_kind) \
+ { \
+ LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
+ LLDB_INVALID_REGNUM, lldb_kind \
+ }
+
+// Generates register kinds array for vector registers
+#define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
+
+// FPR register kinds array for vector registers
+#define FPR64_KIND(reg, generic_kind) MISC_KIND(reg, fpr, generic_kind)
+
+#define MISC_FPR_KIND(lldb_kind) LLDB_KIND(lldb_kind)
+
+// Defines a 64-bit general purpose register
+#define DEFINE_GPR64(reg, generic_kind) \
+ { \
+#reg, nullptr, 8, GPR_OFFSET(gpr_##reg), lldb::eEncodingUint, \
+ lldb::eFormatHex, GPR64_KIND(reg, generic_kind), nullptr, nullptr \
+ }
+
+// Defines a 64-bit general purpose register
+#define DEFINE_GPR64_ALT(reg, alt, generic_kind) \
+ { \
+#reg, #alt, 8, GPR_OFFSET(gpr_##reg), lldb::eEncodingUint, \
+ lldb::eFormatHex, GPR64_KIND(reg, generic_kind), nullptr, nullptr \
+ }
+
+#define DEFINE_FPR64(reg, generic_kind) \
+ { \
+#reg, nullptr, 8, FPR_OFFSET(fpr_##reg - fpr_f0), lldb::eEncodingUint, \
+ lldb::eFormatHex, FPR64_KIND(reg, generic_kind), nullptr, nullptr, \
+ }
+
+// Defines miscellaneous status and control registers like fcsr
+#define DEFINE_MISC_REGS(reg, size, TYPE, lldb_kind) \
+ { \
+#reg, nullptr, size, TYPE##_OFFSET_NAME(reg), lldb::eEncodingUint, \
+ lldb::eFormatHex, MISC_##TYPE##_KIND(lldb_kind), nullptr, nullptr \
+ }
+
+static lldb_private::RegisterInfo g_register_infos_riscv64_le[] = {
+ // DEFINE_GPR64(name, GENERIC KIND)
+ DEFINE_GPR64(x0, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64_ALT(ra, x1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_GPR64_ALT(sp, x2, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GPR64(x3, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x4, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x5, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x6, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x7, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64_ALT(fp, x8, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_GPR64(x9, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x10, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GPR64(x11, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GPR64(x12, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GPR64(x13, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GPR64(x14, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GPR64(x15, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GPR64(x16, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GPR64(x17, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_GPR64(x18, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x19, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x20, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x21, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x22, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x23, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x24, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x25, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x26, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x27, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x28, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x29, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x30, LLDB_INVALID_REGNUM),
+ DEFINE_GPR64(x31, LLDB_INVALID_REGNUM),
+
+ DEFINE_FPR64(f0, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f1, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f2, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f3, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f4, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f5, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f6, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f7, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f8, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f9, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f10, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f11, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f12, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f13, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f14, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f15, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f16, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f17, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f18, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f19, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f20, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f21, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f22, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f23, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f24, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f25, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f26, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f27, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f28, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f29, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f30, LLDB_INVALID_REGNUM),
+ DEFINE_FPR64(f31, LLDB_INVALID_REGNUM),
+
+ DEFINE_MISC_REGS(fcsr, 4, FPR, fpr_fcsr),
+
+ // clang-format on
+};
+
+#endif // DECLARE_REGISTER_INFOS_RISCV64_STRUCT
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h
@@ -0,0 +1,65 @@
+//===-- RegisterInfoPOSIX_riscv64.h -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV64_H
+
+#include "RegisterInfoAndSetInterface.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/lldb-private.h"
+#include <map>
+
+class RegisterInfoPOSIX_riscv64
+ : public lldb_private::RegisterInfoAndSetInterface {
+public:
+ enum { GPRegSet = 0, FPRegSet };
+
+ LLVM_PACKED_START
+ struct GPR {
+ uint64_t zero;
+ uint64_t ra;
+ uint64_t sp;
+ uint64_t gp;
+ uint64_t tp;
+ uint64_t t[7]; // t0-6
+ uint64_t s[12]; // fp/s0-s11
+ uint64_t a[8]; // a0-7
+ };
+ LLVM_PACKED_END
+
+ struct FPR {
+ uint64_t f[32];
+ uint32_t fcsr;
+ };
+
+ RegisterInfoPOSIX_riscv64(const lldb_private::ArchSpec &target_arch,
+ lldb_private::Flags flags);
+
+ size_t GetGPRSize() const override;
+
+ size_t GetFPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ const lldb_private::RegisterSet *
+ GetRegisterSet(size_t reg_set) const override;
+
+ size_t GetRegisterSetCount() const override;
+
+ size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
+
+ uint32_t GetRegNumFCSR() const;
+
+private:
+ const lldb_private::RegisterInfo *m_register_info_p;
+ uint32_t m_register_info_count;
+};
+
+#endif
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
@@ -0,0 +1,163 @@
+//===-- RegisterInfoPOSIX_riscv64.cpp -------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include <cassert>
+#include <lldb/Utility/Flags.h>
+#include <stddef.h>
+
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Compiler.h"
+
+#include "RegisterInfoPOSIX_riscv64.h"
+
+#define GPR_OFFSET(idx) ((idx)*8)
+#define GPR_OFFSET_NAME(reg) \
+ (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_riscv64::GPR, reg))
+
+#define FPR_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_riscv64::GPR))
+#define FPR_OFFSET_NAME(reg) \
+ (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_riscv64::FPR, reg) + \
+ sizeof(RegisterInfoPOSIX_riscv64::GPR))
+
+#define DBG_OFFSET_NAME(reg) \
+ (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_riscv64::DBG, reg) + \
+ sizeof(RegisterInfoPOSIX_riscv64::GPR) + \
+ sizeof(RegisterInfoPOSIX_riscv64::FPR))
+
+#define DEFINE_DBG(reg, i) \
+#reg, NULL, sizeof(((RegisterInfoPOSIX_riscv64::DBG *)NULL)->reg[i]), \
+ DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
+ LLDB_INVALID_REGNUM, dbg_##reg##i }, \
+ NULL, NULL, NULL, 0
+#define REG_CONTEXT_SIZE \
+ (sizeof(RegisterInfoPOSIX_riscv64::GPR) + \
+ sizeof(RegisterInfoPOSIX_riscv64::FPR))
+
+#define DECLARE_REGISTER_INFOS_RISCV64_STRUCT
+#include "RegisterInfos_riscv64.h"
+#undef DECLARE_REGISTER_INFOS_RISCV64_STRUCT
+
+static const lldb_private::RegisterInfo *
+GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::riscv64:
+ return g_register_infos_riscv64_le;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+// Number of register sets provided by this context.
+enum {
+ k_num_gpr_registers = gpr_x31 - gpr_x0 + 1,
+ k_num_fpr_registers = fpr_fcsr - fpr_f0 + 1,
+ k_num_register_sets = 2
+};
+
+// RISC-V64 general purpose registers.
+static const uint32_t g_gpr_regnums_riscv64[] = {
+ gpr_x0, gpr_ra, gpr_sp,
+ gpr_x3, gpr_x4, gpr_x5,
+ gpr_x6, gpr_x7, gpr_fp,
+ gpr_x9, gpr_x10, gpr_x11,
+ gpr_x12, gpr_x13, gpr_x14,
+ gpr_x15, gpr_x16, gpr_x17,
+ gpr_x18, gpr_x19, gpr_x20,
+ gpr_x21, gpr_x22, gpr_x23,
+ gpr_x24, gpr_x25, gpr_x26,
+ gpr_x27, gpr_x28, gpr_x29,
+ gpr_x30, gpr_x31, LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_gpr_regnums_riscv64 /
+ sizeof g_gpr_regnums_riscv64[0]) -
+ 1) == k_num_gpr_registers,
+ "g_gpr_regnums_riscv64 has wrong number of register infos");
+
+// RISC-V64 floating point registers.
+static const uint32_t g_fpr_regnums_riscv64[] = {
+ fpr_f0, fpr_f1, fpr_f2, fpr_f3, fpr_f4, fpr_f5,
+ fpr_f6, fpr_f7, fpr_f8, fpr_f9, fpr_f10, fpr_f11,
+ fpr_f12, fpr_f13, fpr_f14, fpr_f15, fpr_f16, fpr_f17,
+ fpr_f18, fpr_f19, fpr_f20, fpr_f21, fpr_f22, fpr_f23,
+ fpr_f24, fpr_f25, fpr_f26, fpr_f27, fpr_f28, fpr_f29,
+ fpr_f30, fpr_f31, fpr_d0, fpr_d1, fpr_d2, fpr_d3,
+ fpr_d4, fpr_d5, fpr_d6, fpr_d7, fpr_d8, fpr_d9,
+ fpr_d10, fpr_d11, fpr_d12, fpr_d13, fpr_d14, fpr_d15,
+ fpr_d16, fpr_d17, fpr_d18, fpr_d19, fpr_d20, fpr_d21,
+ fpr_d22, fpr_d23, fpr_d24, fpr_d25, fpr_d26, fpr_d27,
+ fpr_d28, fpr_d29, fpr_d30, fpr_d31, fpr_fcsr, LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_fpr_regnums_riscv64 /
+ sizeof g_fpr_regnums_riscv64[0]) -
+ 1) == k_num_fpr_registers,
+ "g_fpr_regnums_riscv64 has wrong number of register infos");
+
+// Register sets for RISC-V64.
+static const lldb_private::RegisterSet g_reg_sets_riscv64[k_num_register_sets] =
+ {{"General Purpose Registers", "gpr", k_num_gpr_registers,
+ g_gpr_regnums_riscv64},
+ {"Floating Point Registers", "fpr", k_num_fpr_registers,
+ g_fpr_regnums_riscv64}};
+
+static uint32_t
+GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::riscv64:
+ return static_cast<uint32_t>(sizeof(g_register_infos_riscv64_le) /
+ sizeof(g_register_infos_riscv64_le[0]));
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+RegisterInfoPOSIX_riscv64::RegisterInfoPOSIX_riscv64(
+ const lldb_private::ArchSpec &target_arch, lldb_private::Flags flags)
+ : lldb_private::RegisterInfoAndSetInterface(target_arch),
+ m_register_info_p(GetRegisterInfoPtr(target_arch)),
+ m_register_info_count(GetRegisterInfoCount(target_arch)) {}
+
+uint32_t RegisterInfoPOSIX_riscv64::GetRegisterCount() const {
+ return k_num_gpr_registers;
+}
+
+size_t RegisterInfoPOSIX_riscv64::GetGPRSize() const {
+ return sizeof(struct RegisterInfoPOSIX_riscv64::GPR);
+}
+
+size_t RegisterInfoPOSIX_riscv64::GetFPRSize() const {
+ return sizeof(struct RegisterInfoPOSIX_riscv64::FPR);
+}
+
+const lldb_private::RegisterInfo *
+RegisterInfoPOSIX_riscv64::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+size_t RegisterInfoPOSIX_riscv64::GetRegisterSetCount() const {
+ return k_num_register_sets - 1;
+}
+
+size_t RegisterInfoPOSIX_riscv64::GetRegisterSetFromRegisterIndex(
+ uint32_t reg_index) const {
+ if (reg_index <= gpr_x31)
+ return GPRegSet;
+ if (reg_index >= gpr_x31 && reg_index <= fpr_fcsr)
+ return FPRegSet;
+ return LLDB_INVALID_REGNUM;
+}
+
+const lldb_private::RegisterSet *
+RegisterInfoPOSIX_riscv64::GetRegisterSet(size_t set_index) const {
+ if (set_index < GetRegisterSetCount())
+ return &g_reg_sets_riscv64[set_index];
+ return nullptr;
+}
+uint32_t RegisterInfoPOSIX_riscv64::GetRegNumFCSR() const { return fpr_fcsr; }
Index: lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h
@@ -0,0 +1,62 @@
+//===-- RegisterContextPOSIX_riscv64.h --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV64_H
+
+#include "RegisterInfoInterface.h"
+#include "RegisterInfoPOSIX_riscv64.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Utility/Log.h"
+
+class RegisterContextPOSIX_riscv64 : public lldb_private::RegisterContext {
+public:
+ RegisterContextPOSIX_riscv64(
+ lldb_private::Thread &thread,
+ std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info);
+
+ ~RegisterContextPOSIX_riscv64() override;
+
+ void invalidate();
+
+ void InvalidateAllRegisters() override;
+
+ size_t GetRegisterCount() override;
+
+ virtual size_t GetGPRSize();
+
+ virtual unsigned GetRegisterSize(unsigned reg);
+
+ virtual unsigned GetRegisterOffset(unsigned reg);
+
+ const lldb_private::RegisterInfo *GetRegisterInfoAtIndex(size_t reg) override;
+
+ size_t GetRegisterSetCount() override;
+
+ const lldb_private::RegisterSet *GetRegisterSet(size_t set) override;
+
+protected:
+ std::unique_ptr<RegisterInfoPOSIX_riscv64> m_register_info_up;
+
+ virtual const lldb_private::RegisterInfo *GetRegisterInfo();
+
+ bool IsGPR(unsigned reg);
+
+ bool IsFPR(unsigned reg);
+
+ size_t GetFPRSize() { return sizeof(RegisterInfoPOSIX_riscv64::FPR); }
+
+ uint32_t GetRegNumFCSR() const { return m_register_info_up->GetRegNumFCSR(); }
+
+ virtual bool ReadGPR() = 0;
+ virtual bool ReadFPR() = 0;
+ virtual bool WriteGPR() = 0;
+ virtual bool WriteFPR() = 0;
+};
+
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV64_H
Index: lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
@@ -0,0 +1,90 @@
+//===-- RegisterContextPOSIX_riscv64.cpp ------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include <cerrno>
+#include <cstdint>
+#include <cstring>
+
+#include "lldb/Target/Process.h"
+#include "lldb/Target/Target.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/DataBufferHeap.h"
+#include "lldb/Utility/DataExtractor.h"
+#include "lldb/Utility/Endian.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/Utility/Scalar.h"
+#include "llvm/Support/Compiler.h"
+
+#include "RegisterContextPOSIX_riscv64.h"
+
+using namespace lldb;
+using namespace lldb_private;
+
+RegisterContextPOSIX_riscv64::RegisterContextPOSIX_riscv64(
+ lldb_private::Thread &thread,
+ std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info)
+ : lldb_private::RegisterContext(thread, 0),
+ m_register_info_up(std::move(register_info)) {}
+
+RegisterContextPOSIX_riscv64::~RegisterContextPOSIX_riscv64() = default;
+
+void RegisterContextPOSIX_riscv64::invalidate() {}
+
+void RegisterContextPOSIX_riscv64::InvalidateAllRegisters() {}
+
+size_t RegisterContextPOSIX_riscv64::GetRegisterCount() {
+ return m_register_info_up->GetRegisterCount();
+}
+
+size_t RegisterContextPOSIX_riscv64::GetGPRSize() {
+ return m_register_info_up->GetGPRSize();
+}
+
+unsigned RegisterContextPOSIX_riscv64::GetRegisterSize(unsigned int reg) {
+ return m_register_info_up->GetRegisterInfo()[reg].byte_size;
+}
+
+unsigned RegisterContextPOSIX_riscv64::GetRegisterOffset(unsigned int reg) {
+ return m_register_info_up->GetRegisterInfo()[reg].byte_offset;
+}
+
+const lldb_private::RegisterInfo *
+RegisterContextPOSIX_riscv64::GetRegisterInfoAtIndex(size_t reg) {
+ if (reg < GetRegisterCount())
+ return &GetRegisterInfo()[reg];
+
+ return nullptr;
+}
+
+size_t RegisterContextPOSIX_riscv64::GetRegisterSetCount() {
+ return m_register_info_up->GetRegisterCount();
+}
+
+const lldb_private::RegisterSet *
+RegisterContextPOSIX_riscv64::GetRegisterSet(size_t set) {
+ return m_register_info_up->GetRegisterSet(set);
+}
+
+const lldb_private::RegisterInfo *
+RegisterContextPOSIX_riscv64::GetRegisterInfo() {
+ return m_register_info_up->GetRegisterInfo();
+}
+
+bool RegisterContextPOSIX_riscv64::IsGPR(unsigned int reg) {
+ if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
+ RegisterInfoPOSIX_riscv64::GPRegSet)
+ return true;
+ return false;
+}
+
+bool RegisterContextPOSIX_riscv64::IsFPR(unsigned int reg) {
+ if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
+ RegisterInfoPOSIX_riscv64::FPRegSet)
+ return true;
+ return false;
+}
Index: lldb/source/Plugins/Process/Utility/CMakeLists.txt
===================================================================
--- lldb/source/Plugins/Process/Utility/CMakeLists.txt
+++ lldb/source/Plugins/Process/Utility/CMakeLists.txt
@@ -41,6 +41,7 @@
RegisterContextPOSIX_mips64.cpp
RegisterContextPOSIX_powerpc.cpp
RegisterContextPOSIX_ppc64le.cpp
+ RegisterContextPOSIX_riscv64.cpp
RegisterContextPOSIX_s390x.cpp
RegisterContextPOSIX_x86.cpp
RegisterContextThreadMemory.cpp
@@ -49,6 +50,7 @@
RegisterInfoPOSIX_arm.cpp
RegisterInfoPOSIX_arm64.cpp
RegisterInfoPOSIX_ppc64le.cpp
+ RegisterInfoPOSIX_riscv64.cpp
StopInfoMachException.cpp
ThreadMemory.cpp
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
@@ -0,0 +1,111 @@
+//===-- NativeRegisterContextLinux_riscv64.h -------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#if defined(__riscv) && __riscv_xlen == 64
+
+#ifndef lldb_NativeRegisterContextLinux_riscv64_h
+#define lldb_NativeRegisterContextLinux_riscv64_h
+
+#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+
+#include <asm/ptrace.h>
+
+namespace lldb_private {
+namespace process_linux {
+
+class NativeProcessLinux;
+
+class NativeRegisterContextLinux_riscv64 : public NativeRegisterContextLinux {
+public:
+ NativeRegisterContextLinux_riscv64(
+ const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
+ std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info_up);
+
+ uint32_t GetRegisterSetCount() const override;
+
+ uint32_t GetUserRegisterCount() const override;
+
+ const RegisterSet *GetRegisterSet(uint32_t set_index) const override;
+
+ Status ReadRegister(const RegisterInfo *reg_info,
+ RegisterValue ®_value) override;
+
+ Status WriteRegister(const RegisterInfo *reg_info,
+ const RegisterValue ®_value) override;
+
+ Status ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override;
+
+ Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
+
+ void InvalidateAllRegisters() override;
+
+ std::vector<uint32_t>
+ GetExpeditedRegisters(ExpeditedRegs expType) const override;
+
+ bool RegisterOffsetIsDynamic() const override { return true; }
+
+protected:
+ Status ReadGPR() override;
+
+ Status WriteGPR() override;
+
+ Status ReadFPR() override;
+
+ Status WriteFPR() override;
+
+ void *GetGPRBuffer() override { return &m_gpr_riscv64; }
+
+ // GetGPRBufferSize returns sizeof riscv64 GPR ptrace buffer, it is different
+ // from GetGPRSize which returns sizeof RegisterInfoPOSIX_riscv64::GPR.
+ size_t GetGPRBufferSize() { return sizeof(m_gpr_riscv64); }
+
+ void *GetFPRBuffer() override { return &m_fpr; }
+
+ size_t GetFPRSize() override { return sizeof(m_fpr); }
+
+private:
+ bool m_gpr_is_valid;
+ bool m_fpu_is_valid;
+
+ struct user_regs_struct m_gpr_riscv64; // 64-bit general purpose registers.
+
+ RegisterInfoPOSIX_riscv64::FPR
+ m_fpr; // floating-point registers including extended register sets.
+
+ // Debug register info for hardware breakpoints and watchpoints management.
+ struct DREG {
+ lldb::addr_t address; // Breakpoint/watchpoint address value.
+ lldb::addr_t hit_addr; // Address at which last watchpoint trigger exception
+ // occurred.
+ lldb::addr_t real_addr; // Address value that should cause target to stop.
+ uint32_t control; // Breakpoint/watchpoint control value.
+ uint32_t refcount; // Serves as enable/disable and reference counter.
+ };
+
+ struct DREG m_hbr_regs[16]; // RISC-V native linux hardware breakpoints
+ struct DREG m_hwp_regs[16]; // RISC-V native linux hardware watchpoints
+
+ uint32_t m_max_hwp_supported;
+ uint32_t m_max_hbp_supported;
+
+ bool IsGPR(unsigned reg) const;
+
+ bool IsFPR(unsigned reg) const;
+
+ uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;
+
+ RegisterInfoPOSIX_riscv64 &GetRegisterInfo() const;
+};
+
+} // namespace process_linux
+} // namespace lldb_private
+
+#endif // #ifndef lldb_NativeRegisterContextLinux_riscv64_h
+
+#endif // defined(__riscv) && __riscv_xlen == 64
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
@@ -0,0 +1,340 @@
+//===-- NativeRegisterContextLinux_riscv64.cpp ----------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#if defined(__riscv) && __riscv_xlen == 64
+
+#include "NativeRegisterContextLinux_riscv64.h"
+
+#include "lldb/Utility/DataBufferHeap.h"
+#include "lldb/Utility/Log.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/Utility/Status.h"
+
+#include "Plugins/Process/Linux/NativeProcessLinux.h"
+#include "Plugins/Process/Linux/Procfs.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+
+// System includes - They have to be included after framework includes because
+// they define some macros which collide with variable names in other modules
+#include <sys/socket.h>
+// NT_PRSTATUS and NT_FPREGSET definition
+#include <elf.h>
+
+#define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize())
+
+using namespace lldb;
+using namespace lldb_private;
+using namespace lldb_private::process_linux;
+
+std::unique_ptr<NativeRegisterContextLinux>
+NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
+ const ArchSpec &target_arch, NativeThreadLinux &native_thread) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::riscv64: {
+ Flags opt_regsets;
+ auto register_info_up =
+ std::make_unique<RegisterInfoPOSIX_riscv64>(target_arch, opt_regsets);
+ return std::make_unique<NativeRegisterContextLinux_riscv64>(
+ target_arch, native_thread, std::move(register_info_up));
+ }
+ default:
+ llvm_unreachable("have no register context for architecture");
+ }
+}
+
+NativeRegisterContextLinux_riscv64::NativeRegisterContextLinux_riscv64(
+ const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
+ std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info_up)
+ : NativeRegisterContextRegisterInfo(native_thread,
+ register_info_up.release()),
+ NativeRegisterContextLinux(native_thread) {
+ ::memset(&m_fpr, 0, sizeof(m_fpr));
+ ::memset(&m_gpr_riscv64, 0, sizeof(m_gpr_riscv64));
+ ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs));
+ ::memset(&m_hbr_regs, 0, sizeof(m_hbr_regs));
+
+ // 16 is just a maximum value, query hardware for actual watchpoint count
+ m_max_hwp_supported = 16;
+ m_max_hbp_supported = 16;
+
+ m_gpr_is_valid = false;
+ m_fpu_is_valid = false;
+}
+
+RegisterInfoPOSIX_riscv64 &
+NativeRegisterContextLinux_riscv64::GetRegisterInfo() const {
+ return static_cast<RegisterInfoPOSIX_riscv64 &>(
+ *m_register_info_interface_up);
+}
+
+uint32_t NativeRegisterContextLinux_riscv64::GetRegisterSetCount() const {
+ return GetRegisterInfo().GetRegisterSetCount();
+}
+
+const RegisterSet *
+NativeRegisterContextLinux_riscv64::GetRegisterSet(uint32_t set_index) const {
+ return GetRegisterInfo().GetRegisterSet(set_index);
+}
+
+uint32_t NativeRegisterContextLinux_riscv64::GetUserRegisterCount() const {
+ uint32_t count = 0;
+ for (uint32_t set_index = 0; set_index < GetRegisterSetCount(); ++set_index)
+ count += GetRegisterSet(set_index)->num_registers;
+ return count;
+}
+
+Status
+NativeRegisterContextLinux_riscv64::ReadRegister(const RegisterInfo *reg_info,
+ RegisterValue ®_value) {
+ Status error;
+
+ if (!reg_info) {
+ error.SetErrorString("reg_info NULL");
+ return error;
+ }
+
+ const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
+
+ if (reg == LLDB_INVALID_REGNUM)
+ return Status("no lldb regnum for %s", reg_info && reg_info->name
+ ? reg_info->name
+ : "<unknown register>");
+
+ uint8_t *src;
+ uint32_t offset = LLDB_INVALID_INDEX32;
+
+ if (IsGPR(reg)) {
+ error = ReadGPR();
+ if (error.Fail())
+ return error;
+
+ offset = reg_info->byte_offset;
+ assert(offset < GetGPRSize());
+ src = (uint8_t *)GetGPRBuffer() + offset;
+
+ } else if (IsFPR(reg)) {
+ error = ReadFPR();
+ if (error.Fail())
+ return error;
+
+ offset = CalculateFprOffset(reg_info);
+ assert(offset < GetFPRSize());
+ src = (uint8_t *)GetFPRBuffer() + offset;
+ } else
+ return Status("failed - register wasn't recognized to be a GPR or an FPR, "
+ "write strategy unknown");
+
+ reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size,
+ eByteOrderLittle, error);
+
+ return error;
+}
+
+Status NativeRegisterContextLinux_riscv64::WriteRegister(
+ const RegisterInfo *reg_info, const RegisterValue ®_value) {
+ Status error;
+
+ if (!reg_info)
+ return Status("reg_info NULL");
+
+ const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
+
+ if (reg == LLDB_INVALID_REGNUM)
+ return Status("no lldb regnum for %s", reg_info->name != nullptr
+ ? reg_info->name
+ : "<unknown register>");
+
+ uint8_t *dst = nullptr;
+ uint32_t offset = LLDB_INVALID_INDEX32;
+ std::vector<uint8_t> sve_reg_non_live;
+
+ if (IsGPR(reg)) {
+ error = ReadGPR();
+ if (error.Fail())
+ return error;
+
+ assert(reg_info->byte_offset < GetGPRSize());
+ dst = (uint8_t *)GetGPRBuffer() + reg_info->byte_offset;
+ ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
+
+ return WriteGPR();
+ } else if (IsFPR(reg)) {
+ // SVE is disabled take legacy route for FPU register access
+ error = ReadFPR();
+ if (error.Fail())
+ return error;
+
+ offset = CalculateFprOffset(reg_info);
+ assert(offset < GetFPRSize());
+ dst = (uint8_t *)GetFPRBuffer() + offset;
+ ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
+
+ return WriteFPR();
+ }
+
+ return Status("Failed to write register value");
+}
+
+Status NativeRegisterContextLinux_riscv64::ReadAllRegisterValues(
+ lldb::WritableDataBufferSP &data_sp) {
+ Status error;
+
+ data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0));
+
+ error = ReadGPR();
+ if (error.Fail())
+ return error;
+
+ error = ReadFPR();
+ if (error.Fail())
+ return error;
+
+ uint8_t *dst = const_cast<uint8_t *>(data_sp->GetBytes());
+ ::memcpy(dst, GetGPRBuffer(), GetGPRSize());
+ dst += GetGPRSize();
+ ::memcpy(dst, GetFPRBuffer(), GetFPRSize());
+
+ return error;
+}
+
+Status NativeRegisterContextLinux_riscv64::WriteAllRegisterValues(
+ const lldb::DataBufferSP &data_sp) {
+ Status error;
+
+ if (!data_sp) {
+ error.SetErrorStringWithFormat(
+ "NativeRegisterContextLinux_x86_64::%s invalid data_sp provided",
+ __FUNCTION__);
+ return error;
+ }
+
+ if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) {
+ error.SetErrorStringWithFormat(
+ "NativeRegisterContextLinux_x86_64::%s data_sp contained mismatched "
+ "data size, expected %" PRIu64 ", actual %" PRIu64,
+ __FUNCTION__, REG_CONTEXT_SIZE, data_sp->GetByteSize());
+ return error;
+ }
+
+ uint8_t *src = const_cast<uint8_t *>(data_sp->GetBytes());
+ if (src == nullptr) {
+ error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s "
+ "DataBuffer::GetBytes() returned a null "
+ "pointer",
+ __FUNCTION__);
+ return error;
+ }
+ ::memcpy(GetGPRBuffer(), src, GetRegisterInfoInterface().GetGPRSize());
+
+ error = WriteGPR();
+ if (error.Fail())
+ return error;
+
+ src += GetRegisterInfoInterface().GetGPRSize();
+ ::memcpy(GetFPRBuffer(), src, GetFPRSize());
+
+ error = WriteFPR();
+ if (error.Fail())
+ return error;
+
+ return error;
+}
+
+bool NativeRegisterContextLinux_riscv64::IsGPR(unsigned reg) const {
+ return GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
+ RegisterInfoPOSIX_riscv64::GPRegSet;
+}
+
+bool NativeRegisterContextLinux_riscv64::IsFPR(unsigned reg) const {
+ return GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
+ RegisterInfoPOSIX_riscv64::FPRegSet;
+}
+
+Status NativeRegisterContextLinux_riscv64::ReadGPR() {
+ Status error;
+
+ if (m_gpr_is_valid)
+ return error;
+
+ struct iovec ioVec;
+ ioVec.iov_base = GetGPRBuffer();
+ ioVec.iov_len = GetGPRBufferSize();
+
+ error = ReadRegisterSet(&ioVec, GetGPRBufferSize(), NT_PRSTATUS);
+
+ if (error.Success())
+ m_gpr_is_valid = true;
+
+ return error;
+}
+
+Status NativeRegisterContextLinux_riscv64::WriteGPR() {
+ Status error = ReadGPR();
+ if (error.Fail())
+ return error;
+
+ struct iovec ioVec;
+ ioVec.iov_base = GetGPRBuffer();
+ ioVec.iov_len = GetGPRBufferSize();
+
+ m_gpr_is_valid = false;
+
+ return WriteRegisterSet(&ioVec, GetGPRBufferSize(), NT_PRSTATUS);
+}
+
+Status NativeRegisterContextLinux_riscv64::ReadFPR() {
+ Status error;
+
+ if (m_fpu_is_valid)
+ return error;
+
+ struct iovec ioVec;
+ ioVec.iov_base = GetFPRBuffer();
+ ioVec.iov_len = GetFPRSize();
+
+ error = ReadRegisterSet(&ioVec, GetFPRSize(), NT_FPREGSET);
+
+ if (error.Success())
+ m_fpu_is_valid = true;
+
+ return error;
+}
+
+Status NativeRegisterContextLinux_riscv64::WriteFPR() {
+ Status error = ReadFPR();
+ if (error.Fail())
+ return error;
+
+ struct iovec ioVec;
+ ioVec.iov_base = GetFPRBuffer();
+ ioVec.iov_len = GetFPRSize();
+
+ m_fpu_is_valid = false;
+
+ return WriteRegisterSet(&ioVec, GetFPRSize(), NT_FPREGSET);
+}
+
+void NativeRegisterContextLinux_riscv64::InvalidateAllRegisters() {
+ m_gpr_is_valid = false;
+ m_fpu_is_valid = false;
+}
+
+uint32_t NativeRegisterContextLinux_riscv64::CalculateFprOffset(
+ const RegisterInfo *reg_info) const {
+ return reg_info->byte_offset - GetGPRSize();
+}
+
+std::vector<uint32_t> NativeRegisterContextLinux_riscv64::GetExpeditedRegisters(
+ ExpeditedRegs expType) const {
+ std::vector<uint32_t> expedited_reg_nums =
+ NativeRegisterContext::GetExpeditedRegisters(expType);
+
+ return expedited_reg_nums;
+}
+
+#endif // defined (__riscv) && __riscv_xlen == 64
Index: lldb/source/Plugins/Process/Linux/CMakeLists.txt
===================================================================
--- lldb/source/Plugins/Process/Linux/CMakeLists.txt
+++ lldb/source/Plugins/Process/Linux/CMakeLists.txt
@@ -9,6 +9,7 @@
NativeRegisterContextLinux_arm.cpp
NativeRegisterContextLinux_arm64.cpp
NativeRegisterContextLinux_ppc64le.cpp
+ NativeRegisterContextLinux_riscv64.cpp
NativeRegisterContextLinux_s390x.cpp
NativeRegisterContextLinux_x86_64.cpp
NativeThreadLinux.cpp
Index: lldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp
===================================================================
--- lldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp
+++ lldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp
@@ -1226,6 +1226,8 @@
case llvm::COFF::IMAGE_FILE_MACHINE_ARMNT:
case llvm::COFF::IMAGE_FILE_MACHINE_THUMB:
case llvm::COFF::IMAGE_FILE_MACHINE_ARM64:
+ case llvm::COFF::IMAGE_FILE_MACHINE_RISCV32:
+ case llvm::COFF::IMAGE_FILE_MACHINE_RISCV64:
ArchSpec arch;
arch.SetArchitecture(eArchTypeCOFF, machine, LLDB_INVALID_CPUTYPE,
IsWindowsSubsystem() ? llvm::Triple::Win32
Index: lldb/source/Plugins/Architecture/RISCV64/CMakeLists.txt
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Architecture/RISCV64/CMakeLists.txt
@@ -0,0 +1,11 @@
+add_lldb_library(lldbPluginArchitectureRISCV64 PLUGIN
+ ArchitectureRISCV64.cpp
+
+ LINK_LIBS
+ lldbPluginProcessUtility
+ lldbCore
+ lldbTarget
+ lldbUtility
+ LINK_COMPONENTS
+ Support
+ )
Index: lldb/source/Plugins/Architecture/RISCV64/ArchitectureRISCV64.h
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Architecture/RISCV64/ArchitectureRISCV64.h
@@ -0,0 +1,39 @@
+//===-- ArchitectureRISCV64.h -----------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_ARCHITECTURE_RISCV64_ARCHITECTUREPRISCV64_H
+#define LLDB_SOURCE_PLUGINS_ARCHITECTURE_RISCV64_ARCHITECTUREPRISCV64_H
+
+#include "lldb/Core/Architecture.h"
+
+namespace lldb_private {
+
+class ArchitectureRISCV64 : public Architecture {
+public:
+ static llvm::StringRef GetPluginNameStatic() { return "riscv64"; }
+ static void Initialize();
+ static void Terminate();
+
+ llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
+
+ lldb::addr_t GetCallableLoadAddress(lldb::addr_t load_addr,
+ AddressClass addr_class) const override;
+
+ lldb::addr_t GetOpcodeLoadAddress(lldb::addr_t load_addr,
+ AddressClass addr_class) const override;
+
+ void OverrideStopInfo(Thread &thread) const override {}
+
+private:
+ static std::unique_ptr<Architecture> Create(const ArchSpec &arch);
+ ArchitectureRISCV64() = default;
+};
+
+} // namespace lldb_private
+
+#endif // LLDB_SOURCE_PLUGINS_ARCHITECTURE_RISCV64_ARCHITECTUREPRISCV64_H
Index: lldb/source/Plugins/Architecture/RISCV64/ArchitectureRISCV64.cpp
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Architecture/RISCV64/ArchitectureRISCV64.cpp
@@ -0,0 +1,70 @@
+//===-- ArchitectureRISCV64.cpp ---------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "lldb/Core/Architecture.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/ArchSpec.h"
+
+#include "ArchitectureRISCV64.h"
+
+using namespace lldb_private;
+using namespace lldb;
+
+LLDB_PLUGIN_DEFINE(ArchitectureRISCV64)
+
+void lldb_private::ArchitectureRISCV64::Initialize() {
+ PluginManager::RegisterPlugin(GetPluginNameStatic(), "RISC-V64",
+ &ArchitectureRISCV64::Create);
+}
+
+void ArchitectureRISCV64::Terminate() {
+ PluginManager::UnregisterPlugin(&ArchitectureRISCV64::Create);
+}
+
+std::unique_ptr<Architecture>
+ArchitectureRISCV64::Create(const ArchSpec &arch) {
+ if (arch.GetMachine() != llvm::Triple::riscv64)
+ return nullptr;
+ return std::unique_ptr<Architecture>(new ArchitectureRISCV64());
+}
+
+addr_t
+ArchitectureRISCV64::GetCallableLoadAddress(addr_t code_addr,
+ AddressClass addr_class) const {
+ bool is_alternate_isa = false;
+
+ switch (addr_class) {
+ case AddressClass::eData:
+ case AddressClass::eDebug:
+ return LLDB_INVALID_ADDRESS;
+ case AddressClass::eCodeAlternateISA:
+ is_alternate_isa = true;
+ break;
+ default:
+ break;
+ }
+
+ if ((code_addr & 2ull) || is_alternate_isa)
+ return code_addr | 1u;
+ return code_addr;
+}
+
+addr_t
+ArchitectureRISCV64::GetOpcodeLoadAddress(addr_t opcode_addr,
+ AddressClass addr_class) const {
+ switch (addr_class) {
+ case AddressClass::eData:
+ case AddressClass::eDebug:
+ return LLDB_INVALID_ADDRESS;
+ default:
+ break;
+ }
+ return opcode_addr & ~(1ull);
+}
Index: lldb/source/Plugins/Architecture/RISCV32/CMakeLists.txt
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Architecture/RISCV32/CMakeLists.txt
@@ -0,0 +1,11 @@
+add_lldb_library(lldbPluginArchitectureRISCV32 PLUGIN
+ ArchitectureRISCV32.cpp
+
+ LINK_LIBS
+ lldbPluginProcessUtility
+ lldbCore
+ lldbTarget
+ lldbUtility
+ LINK_COMPONENTS
+ Support
+ )
Index: lldb/source/Plugins/Architecture/RISCV32/ArchitectureRISCV32.h
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Architecture/RISCV32/ArchitectureRISCV32.h
@@ -0,0 +1,39 @@
+//===-- ArchitectureRISCV32.h -----------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_ARCHITECTURE_RISCV32_ARCHITECTUREPRISCV32_H
+#define LLDB_SOURCE_PLUGINS_ARCHITECTURE_RISCV32_ARCHITECTUREPRISCV32_H
+
+#include "lldb/Core/Architecture.h"
+
+namespace lldb_private {
+
+class ArchitectureRISCV32 : public Architecture {
+public:
+ static llvm::StringRef GetPluginNameStatic() { return "riscv32"; }
+ static void Initialize();
+ static void Terminate();
+
+ llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
+
+ lldb::addr_t GetCallableLoadAddress(lldb::addr_t load_addr,
+ AddressClass addr_class) const override;
+
+ lldb::addr_t GetOpcodeLoadAddress(lldb::addr_t load_addr,
+ AddressClass addr_class) const override;
+
+ void OverrideStopInfo(Thread &thread) const override {}
+
+private:
+ static std::unique_ptr<Architecture> Create(const ArchSpec &arch);
+ ArchitectureRISCV32() = default;
+};
+
+} // namespace lldb_private
+
+#endif // LLDB_SOURCE_PLUGINS_ARCHITECTURE_RISCV32_ARCHITECTUREPRISCV32_H
Index: lldb/source/Plugins/Architecture/RISCV32/ArchitectureRISCV32.cpp
===================================================================
--- /dev/null
+++ lldb/source/Plugins/Architecture/RISCV32/ArchitectureRISCV32.cpp
@@ -0,0 +1,70 @@
+//===-- ArchitectureRISCV32.cpp ---------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "lldb/Core/Architecture.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/ArchSpec.h"
+
+#include "ArchitectureRISCV32.h"
+
+using namespace lldb_private;
+using namespace lldb;
+
+LLDB_PLUGIN_DEFINE(ArchitectureRISCV32)
+
+void lldb_private::ArchitectureRISCV32::Initialize() {
+ PluginManager::RegisterPlugin(GetPluginNameStatic(), "RISC-V32",
+ &ArchitectureRISCV32::Create);
+}
+
+void ArchitectureRISCV32::Terminate() {
+ PluginManager::UnregisterPlugin(&ArchitectureRISCV32::Create);
+}
+
+std::unique_ptr<Architecture>
+ArchitectureRISCV32::Create(const ArchSpec &arch) {
+ if (arch.GetMachine() != llvm::Triple::riscv32)
+ return nullptr;
+ return std::unique_ptr<Architecture>(new ArchitectureRISCV32());
+}
+
+addr_t
+ArchitectureRISCV32::GetCallableLoadAddress(addr_t code_addr,
+ AddressClass addr_class) const {
+ bool is_alternate_isa = false;
+
+ switch (addr_class) {
+ case AddressClass::eData:
+ case AddressClass::eDebug:
+ return LLDB_INVALID_ADDRESS;
+ case AddressClass::eCodeAlternateISA:
+ is_alternate_isa = true;
+ break;
+ default:
+ break;
+ }
+
+ if ((code_addr & 2ull) || is_alternate_isa)
+ return code_addr | 1u;
+ return code_addr;
+}
+
+addr_t
+ArchitectureRISCV32::GetOpcodeLoadAddress(addr_t opcode_addr,
+ AddressClass addr_class) const {
+ switch (addr_class) {
+ case AddressClass::eData:
+ case AddressClass::eDebug:
+ return LLDB_INVALID_ADDRESS;
+ default:
+ break;
+ }
+ return opcode_addr & ~(1ull);
+}
Index: lldb/source/Plugins/Architecture/CMakeLists.txt
===================================================================
--- lldb/source/Plugins/Architecture/CMakeLists.txt
+++ lldb/source/Plugins/Architecture/CMakeLists.txt
@@ -2,3 +2,5 @@
add_subdirectory(Mips)
add_subdirectory(PPC64)
add_subdirectory(AArch64)
+add_subdirectory(RISCV32)
+add_subdirectory(RISCV64)
Index: lldb/source/Plugins/ABI/RISCV64/CMakeLists.txt
===================================================================
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV64/CMakeLists.txt
@@ -0,0 +1,10 @@
+add_lldb_library(lldbPluginABIRISCV64 PLUGIN
+ ABISysV_riscv64.cpp
+
+ LINK_LIBS
+ lldbCore
+ lldbSymbol
+ lldbTarget
+ LINK_COMPONENTS
+ Support
+ )
Index: lldb/source/Host/common/HostInfoBase.cpp
===================================================================
--- lldb/source/Host/common/HostInfoBase.cpp
+++ lldb/source/Host/common/HostInfoBase.cpp
@@ -339,6 +339,7 @@
case llvm::Triple::ppc64:
case llvm::Triple::ppc64le:
case llvm::Triple::x86_64:
+ case llvm::Triple::riscv64:
arch_64.SetTriple(triple);
arch_32.SetTriple(triple.get32BitArchVariant());
break;
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