Author: David Spickett Date: 2023-08-31T10:21:53+01:00 New Revision: 6697afe99fb6df08d4c1903eb1df5446f2ec1993
URL: https://github.com/llvm/llvm-project/commit/6697afe99fb6df08d4c1903eb1df5446f2ec1993 DIFF: https://github.com/llvm/llvm-project/commit/6697afe99fb6df08d4c1903eb1df5446f2ec1993.diff LOG: [lldb][AArch64] Check SIMD save/restore in SVE SIMD test While doing some refactoring I forgot to carry over the copying in of SIMD data in normal mode, but no tests failed. Turns out, it's very easy for us to get the restore wrong because even if you forget the memcopy, setting the buffer to valid may just read the data you had before the expression evaluation. So I've extended the SVE SIMD testing (which includes the plain SIMD mode) to check expression save/restore. This is the only test that fails if you forget to do `m_fpu_is_valid = true` so I take from that, that prior to this it wasn't tested at all. As a bonus, we now have coverage of the same thing for SVE and SSVE modes. Reviewed By: omjavaid Differential Revision: https://reviews.llvm.org/D157000 Added: Modified: lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c Removed: ################################################################################ diff --git a/lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py b/lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py index 7b1fa8f9be41f7..c38a255aac6e29 100644 --- a/lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py +++ b/lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py @@ -1,6 +1,6 @@ """ -Test that LLDB correctly reads and writes AArch64 SIMD registers in SVE, -streaming SVE and normal SIMD modes. +Test that LLDB correctly reads and writes and restores AArch64 SIMD registers +in SVE, streaming SVE and normal SIMD modes. There are a few operating modes and we use diff erent strategies for each: * Without SVE, in SIMD mode - read the SIMD regset. @@ -48,6 +48,13 @@ def make_simd_value(self, n): pad = " ".join(["0x00"] * 7) return "{{0x{:02x} {} 0x{:02x} {}}}".format(n, pad, n, pad) + def check_simd_values(self, value_offset): + # These are 128 bit registers, so getting them from the API as unsigned + # values doesn't work. Check the command output instead. + for i in range(32): + self.expect("register read v{}".format(i), + substrs=[self.make_simd_value(i+value_offset)]) + def sve_simd_registers_impl(self, mode): self.skip_if_needed(mode) @@ -68,12 +75,9 @@ def sve_simd_registers_impl(self, mode): substrs=["stop reason = breakpoint 1."], ) - # These are 128 bit registers, so getting them from the API as unsigned - # values doesn't work. Check the command output instead. - for i in range(32): - self.expect( - "register read v{}".format(i), substrs=[self.make_simd_value(i)] - ) + self.check_simd_values(0) + self.runCmd("expression write_simd_regs(1)") + self.check_simd_values(0) # Write a new set of values. The kernel will move the program back to # non-streaming mode here. @@ -83,10 +87,7 @@ def sve_simd_registers_impl(self, mode): ) # Should be visible within lldb. - for i in range(32): - self.expect( - "register read v{}".format(i), substrs=[self.make_simd_value(i + 1)] - ) + self.check_simd_values(1) # The program should agree with lldb. self.expect("continue", substrs=["exited with status = 0"]) diff --git a/lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c b/lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c index 954d84039fb313..2156f094cab5c5 100644 --- a/lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c +++ b/lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c @@ -1,10 +1,11 @@ #include <stdint.h> #include <sys/prctl.h> -void write_simd_regs() { +// base is added to each value. If base = 2, then v0 = 2, v1 = 3, etc. +void write_simd_regs(unsigned base) { #define WRITE_SIMD(NUM) \ asm volatile("MOV v" #NUM ".d[0], %0\n\t" \ - "MOV v" #NUM ".d[1], %0\n\t" ::"r"(NUM)) + "MOV v" #NUM ".d[1], %0\n\t" ::"r"(base + NUM)) WRITE_SIMD(0); WRITE_SIMD(1); @@ -102,7 +103,7 @@ int main() { #endif // else test plain SIMD access. - write_simd_regs(); + write_simd_regs(0); return verify_simd_regs(); // Set a break point here. } _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
