https://github.com/AlexeyMerzlyakov updated
https://github.com/llvm/llvm-project/pull/93297
>From d30c3b7017bd9f4b9f442ee728d7e3d7847c60cf Mon Sep 17 00:00:00 2001
From: Alexey Merzlyakov <alexey.merzlya...@samsung.com>
Date: Fri, 24 May 2024 11:54:16 +0300
Subject: [PATCH 1/4] Add RegisterContextPOSIXCore for RISC-V 64
Fix GetRegisterSetCount() method name misprint for RegisterContextPOSIX_riscv64
---
.../Utility/RegisterContextPOSIX_riscv64.cpp | 2 +-
.../Plugins/Process/elf-core/CMakeLists.txt | 1 +
.../RegisterContextPOSIXCore_riscv64.cpp | 84 +++++++++++++++++++
.../RegisterContextPOSIXCore_riscv64.h | 60 +++++++++++++
.../Process/elf-core/ThreadElfCore.cpp | 8 +-
5 files changed, 153 insertions(+), 2 deletions(-)
create mode 100644
lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
create mode 100644
lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
diff --git
a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
index 1834a94dc0260..035ce00e11626 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
@@ -58,7 +58,7 @@ RegisterContextPOSIX_riscv64::GetRegisterInfoAtIndex(size_t
reg) {
}
size_t RegisterContextPOSIX_riscv64::GetRegisterSetCount() {
- return m_register_info_up->GetRegisterCount();
+ return m_register_info_up->GetRegisterSetCount();
}
const lldb_private::RegisterSet *
diff --git a/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
b/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
index 8ddc671e3ae66..72925c835b5c8 100644
--- a/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
@@ -9,6 +9,7 @@ add_lldb_library(lldbPluginProcessElfCore PLUGIN
RegisterContextPOSIXCore_ppc64le.cpp
RegisterContextPOSIXCore_s390x.cpp
RegisterContextPOSIXCore_x86_64.cpp
+ RegisterContextPOSIXCore_riscv64.cpp
RegisterUtilities.cpp
LINK_LIBS
diff --git
a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
new file mode 100644
index 0000000000000..2202be4d38082
--- /dev/null
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
@@ -0,0 +1,84 @@
+//===-- RegisterContextPOSIXCore_riscv64.cpp
------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "RegisterContextPOSIXCore_riscv64.h"
+
+#include "lldb/Utility/DataBufferHeap.h"
+
+using namespace lldb_private;
+
+std::unique_ptr<RegisterContextCorePOSIX_riscv64>
+RegisterContextCorePOSIX_riscv64::Create(
+ lldb_private::Thread &thread, const lldb_private::ArchSpec &arch,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef<lldb_private::CoreNote> notes) {
+ Flags flags = 0;
+
+ auto register_info_up =
+ std::make_unique<RegisterInfoPOSIX_riscv64>(arch, flags);
+ return std::unique_ptr<RegisterContextCorePOSIX_riscv64>(
+ new RegisterContextCorePOSIX_riscv64(thread, std::move(register_info_up),
+ gpregset, notes));
+}
+
+RegisterContextCorePOSIX_riscv64::RegisterContextCorePOSIX_riscv64(
+ Thread &thread, std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info,
+ const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
+ : RegisterContextPOSIX_riscv64(thread, std::move(register_info)) {
+
+ m_gpr_buffer = std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
+ gpregset.GetByteSize());
+ m_gpr.SetData(m_gpr_buffer);
+ m_gpr.SetByteOrder(gpregset.GetByteOrder());
+
+ ArchSpec arch = m_register_info_up->GetTargetArchitecture();
+ DataExtractor fpregset = getRegset(notes, arch.GetTriple(), FPR_Desc);
+ m_fpr_buffer = std::make_shared<DataBufferHeap>(fpregset.GetDataStart(),
+ fpregset.GetByteSize());
+ m_fpr.SetData(m_fpr_buffer);
+ m_fpr.SetByteOrder(fpregset.GetByteOrder());
+}
+
+RegisterContextCorePOSIX_riscv64::~RegisterContextCorePOSIX_riscv64() =
default;
+
+bool RegisterContextCorePOSIX_riscv64::ReadGPR() { return true; }
+
+bool RegisterContextCorePOSIX_riscv64::ReadFPR() { return true; }
+
+bool RegisterContextCorePOSIX_riscv64::WriteGPR() {
+ assert(0);
+ return false;
+}
+
+bool RegisterContextCorePOSIX_riscv64::WriteFPR() {
+ assert(0);
+ return false;
+}
+
+bool RegisterContextCorePOSIX_riscv64::ReadRegister(
+ const RegisterInfo *reg_info, RegisterValue &value) {
+ const uint8_t *src = nullptr;
+ lldb::offset_t offset = reg_info->byte_offset;
+
+ if (IsGPR(reg_info->kinds[lldb::eRegisterKindLLDB])) {
+ src = m_gpr.GetDataStart();
+ } else { // IsFPR
+ src = m_fpr.GetDataStart();
+ offset -= GetGPRSize();
+ }
+
+ Status error;
+ value.SetFromMemoryData(*reg_info, src + offset, reg_info->byte_size,
+ lldb::eByteOrderLittle, error);
+ return error.Success();
+}
+
+bool RegisterContextCorePOSIX_riscv64::WriteRegister(
+ const RegisterInfo *reg_info, const RegisterValue &value) {
+ return false;
+}
diff --git
a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
new file mode 100644
index 0000000000000..3cf9531df2c1d
--- /dev/null
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
@@ -0,0 +1,60 @@
+//===-- RegisterContextPOSIXCore_riscv64.h ----------------------*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
+
+#include "Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+
+#include "Plugins/Process/elf-core/RegisterUtilities.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/DataExtractor.h"
+#include "lldb/Utility/RegisterValue.h"
+
+#include <memory>
+
+class RegisterContextCorePOSIX_riscv64 : public RegisterContextPOSIX_riscv64 {
+public:
+ static std::unique_ptr<RegisterContextCorePOSIX_riscv64>
+ Create(lldb_private::Thread &thread, const lldb_private::ArchSpec &arch,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef<lldb_private::CoreNote> notes);
+
+ ~RegisterContextCorePOSIX_riscv64() override;
+
+ bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
+ lldb_private::RegisterValue &value) override;
+
+ bool WriteRegister(const lldb_private::RegisterInfo *reg_info,
+ const lldb_private::RegisterValue &value) override;
+
+protected:
+ RegisterContextCorePOSIX_riscv64(
+ lldb_private::Thread &thread,
+ std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef<lldb_private::CoreNote> notes);
+
+ bool ReadGPR() override;
+
+ bool ReadFPR() override;
+
+ bool WriteGPR() override;
+
+ bool WriteFPR() override;
+
+private:
+ lldb::DataBufferSP m_gpr_buffer;
+ lldb::DataBufferSP m_fpr_buffer;
+
+ lldb_private::DataExtractor m_gpr;
+ lldb_private::DataExtractor m_fpr;
+};
+
+#endif //
LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
diff --git a/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
b/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
index 3ce2a4a5c3fa4..2a83163884e16 100644
--- a/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
+++ b/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
@@ -35,6 +35,7 @@
#include "RegisterContextPOSIXCore_mips64.h"
#include "RegisterContextPOSIXCore_powerpc.h"
#include "RegisterContextPOSIXCore_ppc64le.h"
+#include "RegisterContextPOSIXCore_riscv64.h"
#include "RegisterContextPOSIXCore_s390x.h"
#include "RegisterContextPOSIXCore_x86_64.h"
#include "ThreadElfCore.h"
@@ -168,7 +169,8 @@ ThreadElfCore::CreateRegisterContextForFrame(StackFrame
*frame) {
}
if (!reg_interface && arch.GetMachine() != llvm::Triple::aarch64 &&
- arch.GetMachine() != llvm::Triple::arm) {
+ arch.GetMachine() != llvm::Triple::arm &&
+ arch.GetMachine() != llvm::Triple::riscv64) {
LLDB_LOGF(log, "elf-core::%s:: Architecture(%d) or OS(%d) not supported",
__FUNCTION__, arch.GetMachine(), arch.GetTriple().getOS());
assert(false && "Architecture or OS not supported");
@@ -184,6 +186,10 @@ ThreadElfCore::CreateRegisterContextForFrame(StackFrame
*frame) {
*this, std::make_unique<RegisterInfoPOSIX_arm>(arch),
m_gpregset_data,
m_notes);
break;
+ case llvm::Triple::riscv64:
+ m_thread_reg_ctx_sp = RegisterContextCorePOSIX_riscv64::Create(
+ *this, arch, m_gpregset_data, m_notes);
+ break;
case llvm::Triple::mipsel:
case llvm::Triple::mips:
m_thread_reg_ctx_sp = std::make_shared<RegisterContextCorePOSIX_mips64>(
>From 7239f6293ee088a7cde8fa2e6feee00aedf7ac9a Mon Sep 17 00:00:00 2001
From: Alexey Merzlyakov <alexey.merzlya...@samsung.com>
Date: Wed, 29 May 2024 12:29:38 +0300
Subject: [PATCH 2/4] Meet review items
---
.../RegisterContextPOSIXCore_riscv64.cpp | 22 +++++++++----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git
a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
index 2202be4d38082..6f188a9fad5ed 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
@@ -13,17 +13,15 @@
using namespace lldb_private;
std::unique_ptr<RegisterContextCorePOSIX_riscv64>
-RegisterContextCorePOSIX_riscv64::Create(
- lldb_private::Thread &thread, const lldb_private::ArchSpec &arch,
- const lldb_private::DataExtractor &gpregset,
- llvm::ArrayRef<lldb_private::CoreNote> notes) {
+RegisterContextCorePOSIX_riscv64::Create(Thread &thread, const ArchSpec &arch,
+ const DataExtractor &gpregset,
+ llvm::ArrayRef<CoreNote> notes) {
Flags flags = 0;
- auto register_info_up =
- std::make_unique<RegisterInfoPOSIX_riscv64>(arch, flags);
return std::unique_ptr<RegisterContextCorePOSIX_riscv64>(
- new RegisterContextCorePOSIX_riscv64(thread, std::move(register_info_up),
- gpregset, notes));
+ new RegisterContextCorePOSIX_riscv64(
+ thread, std::make_unique<RegisterInfoPOSIX_riscv64>(arch, flags),
+ gpregset, notes));
}
RegisterContextCorePOSIX_riscv64::RegisterContextCorePOSIX_riscv64(
@@ -51,12 +49,12 @@ bool RegisterContextCorePOSIX_riscv64::ReadGPR() { return
true; }
bool RegisterContextCorePOSIX_riscv64::ReadFPR() { return true; }
bool RegisterContextCorePOSIX_riscv64::WriteGPR() {
- assert(0);
+ assert(false && "Writing registers is not allowed for core dumps");
return false;
}
bool RegisterContextCorePOSIX_riscv64::WriteFPR() {
- assert(0);
+ assert(false && "Writing registers is not allowed for core dumps");
return false;
}
@@ -67,9 +65,11 @@ bool RegisterContextCorePOSIX_riscv64::ReadRegister(
if (IsGPR(reg_info->kinds[lldb::eRegisterKindLLDB])) {
src = m_gpr.GetDataStart();
- } else { // IsFPR
+ } else if (IsFPR(reg_info->kinds[lldb::eRegisterKindLLDB])) {
src = m_fpr.GetDataStart();
offset -= GetGPRSize();
+ } else {
+ return false;
}
Status error;
>From 73386d9dffcd902419e33af4ca375fee4998f856 Mon Sep 17 00:00:00 2001
From: Alexey Merzlyakov <alexey.merzlya...@samsung.com>
Date: Tue, 4 Jun 2024 14:51:32 +0300
Subject: [PATCH 3/4] Optimize flags initialization
Add RISC-V 64 testcases to TestLinuxCore.py
---
.../RegisterContextPOSIXCore_riscv64.cpp | 4 +-
.../postmortem/elf-core/TestLinuxCore.py | 57 ++++++++++++++++++
.../postmortem/elf-core/linux-riscv64.core | Bin 0 -> 20480 bytes
.../postmortem/elf-core/linux-riscv64.out | Bin 0 -> 3328 bytes
4 files changed, 58 insertions(+), 3 deletions(-)
create mode 100644
lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.core
create mode 100755
lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.out
diff --git
a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
index 6f188a9fad5ed..5ba18cdb9889a 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
@@ -16,11 +16,9 @@ std::unique_ptr<RegisterContextCorePOSIX_riscv64>
RegisterContextCorePOSIX_riscv64::Create(Thread &thread, const ArchSpec &arch,
const DataExtractor &gpregset,
llvm::ArrayRef<CoreNote> notes) {
- Flags flags = 0;
-
return std::unique_ptr<RegisterContextCorePOSIX_riscv64>(
new RegisterContextCorePOSIX_riscv64(
- thread, std::make_unique<RegisterInfoPOSIX_riscv64>(arch, flags),
+ thread, std::make_unique<RegisterInfoPOSIX_riscv64>(arch, Flags()),
gpregset, notes));
}
diff --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
index 8ec0cbdd0fdd1..4a5cc0819572b 100644
--- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
@@ -21,12 +21,14 @@ class LinuxCoreTestCase(TestBase):
_x86_64_pid = 32259
_s390x_pid = 1045
_ppc64le_pid = 28147
+ _riscv64_pid = 89328
_aarch64_regions = 4
_i386_regions = 4
_x86_64_regions = 5
_s390x_regions = 2
_ppc64le_regions = 2
+ _riscv64_regions = 4
@skipIfLLVMTargetMissing("AArch64")
def test_aarch64(self):
@@ -58,6 +60,11 @@ def test_s390x(self):
"""Test that lldb can read the process information from an s390x linux
core file."""
self.do_test("linux-s390x", self._s390x_pid, self._s390x_regions,
"a.out")
+ @skipIfLLVMTargetMissing("RISCV")
+ def test_riscv64(self):
+ """Test that lldb can read the process information from an riscv64
linux core file."""
+ self.do_test("linux-riscv64", self._riscv64_pid,
self._riscv64_regions, "a.out")
+
@skipIfLLVMTargetMissing("X86")
def test_same_pid_running(self):
"""Test that we read the information from the core correctly even if
we have a running
@@ -629,6 +636,56 @@ def test_arm_core(self):
self.expect("register read --all")
+ @skipIfLLVMTargetMissing("RISCV")
+ def test_riscv64_regs(self):
+ # check basic registers using 64 bit RISC-V core file
+ target = self.dbg.CreateTarget(None)
+ self.assertTrue(target, VALID_TARGET)
+ process = target.LoadCore("linux-riscv64.core")
+
+ values = {}
+ values["pc"] = "0x000000000001015e"
+ values["ra"] = "0x000000000001018c"
+ values["sp"] = "0x0000003fffd132a0"
+ values["gp"] = "0x0000002ae919af50"
+ values["tp"] = "0x0000003fdceae3e0"
+ values["t0"] = "0x0"
+ values["t1"] = "0x0000002ae9187b1c"
+ values["t2"] = "0x0000000000000021"
+ values["fp"] = "0x0000003fffd132d0"
+ values["s1"] = "0x0000002ae919cd98"
+ values["a0"] = "0x0"
+ values["a1"] = "0x0000000000010144"
+ values["a2"] = "0x0000002ae919cdb0"
+ values["a3"] = "0x000000000000002f"
+ values["a4"] = "0x000000000000002f"
+ values["a5"] = "0x0"
+ values["a6"] = "0x7efefefefefefeff"
+ values["a7"] = "0x00000000000000dd"
+ values["s2"] = "0x0000002ae9196860"
+ values["s3"] = "0x0000002ae919cdb0"
+ values["s4"] = "0x0000003fffc63be8"
+ values["s5"] = "0x0000002ae919cb78"
+ values["s6"] = "0x0000002ae9196860"
+ values["s7"] = "0x0000002ae9196860"
+ values["s8"] = "0x0"
+ values["s9"] = "0x000000000000000f"
+ values["s10"] = "0x0000002ae919a8d0"
+ values["s11"] = "0x0000000000000008"
+ values["t3"] = "0x0000003fdce07df4"
+ values["t4"] = "0x0"
+ values["t5"] = "0x0000000000000020"
+ values["t6"] = "0x0000002ae919f1b0"
+ values["zero"] = "0x0"
+
+ for regname, value in values.items():
+ self.expect(
+ "register read {}".format(regname),
+ substrs=["{} = {}".format(regname, value)],
+ )
+
+ self.expect("register read --all")
+
def test_get_core_file_api(self):
"""
Test SBProcess::GetCoreFile() API can successfully get the core file.
diff --git
a/lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.core
b/lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.core
new file mode 100644
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HcmV?d00001
diff --git
a/lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.out
b/lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.out
new file mode 100755
index
0000000000000000000000000000000000000000..ae28aa9ba9aad9700b193281fa8045587c344187
GIT binary patch
literal 3328
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literal 0
HcmV?d00001
>From 183f76dfb73821640cfdf19901703d0a8ff447ff Mon Sep 17 00:00:00 2001
From: Alexey Merzlyakov <alexey.merzlya...@samsung.com>
Date: Wed, 5 Jun 2024 11:38:06 +0300
Subject: [PATCH 4/4] Add FPR check to registers test
---
.../postmortem/elf-core/TestLinuxCore.py | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
index 4a5cc0819572b..0a8fc9c519d8e 100644
--- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
@@ -677,6 +677,14 @@ def test_riscv64_regs(self):
values["t5"] = "0x0000000000000020"
values["t6"] = "0x0000002ae919f1b0"
values["zero"] = "0x0"
+ values["fcsr"] = "0x00000000"
+
+ fpr_names = {"ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
+ "ft8", "ft9", "ft10", "ft11",
+ "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7",
+ "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
+ "fs8", "fs9", "fs10", "fs11"}
+ fpr_value = "0x0000000000000000"
for regname, value in values.items():
self.expect(
@@ -684,6 +692,12 @@ def test_riscv64_regs(self):
substrs=["{} = {}".format(regname, value)],
)
+ for regname in fpr_names:
+ self.expect(
+ "register read {}".format(regname),
+ substrs=["{} = {}".format(regname, fpr_value)],
+ )
+
self.expect("register read --all")
def test_get_core_file_api(self):
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