Author: dsanders Date: Thu Jul 24 04:48:54 2014 New Revision: 213848 URL: http://llvm.org/viewvc/llvm-project?rev=213848&view=rev Log: Merging r213847: ------------------------------------------------------------------------ r213847 | dsanders | 2014-07-24 10:47:14 +0100 (Thu, 24 Jul 2014) | 8 lines
[mips] Fix ll and sc instructions Summary: The ll and sc instructions for r6 and non-r6 are misplaced. This patch fixes that. Patch by Jyun-Yan You Differential Revision: http://reviews.llvm.org/D4578 ------------------------------------------------------------------------ Modified: llvm/branches/release_35/ (props changed) llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp Propchange: llvm/branches/release_35/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Thu Jul 24 04:48:54 2014 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,213653 +/llvm/trunk:155241,213653,213847 Modified: llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp?rev=213848&r1=213847&r2=213848&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp Thu Jul 24 04:48:54 2014 @@ -969,16 +969,16 @@ MipsTargetLowering::emitAtomicBinary(Mac LL = Mips::LL_MM; SC = Mips::SC_MM; } else { - LL = Subtarget.hasMips32r6() ? Mips::LL : Mips::LL_R6; - SC = Subtarget.hasMips32r6() ? Mips::SC : Mips::SC_R6; + LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL; + SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC; } AND = Mips::AND; NOR = Mips::NOR; ZERO = Mips::ZERO; BEQ = Mips::BEQ; } else { - LL = Subtarget.hasMips64r6() ? Mips::LLD : Mips::LLD_R6; - SC = Subtarget.hasMips64r6() ? Mips::SCD : Mips::SCD_R6; + LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; + SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; AND = Mips::AND64; NOR = Mips::NOR64; ZERO = Mips::ZERO_64; _______________________________________________ llvm-branch-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
