Author: dsanders Date: Mon Dec 1 05:32:07 2014 New Revision: 223009 URL: http://llvm.org/viewvc/llvm-project?rev=223009&view=rev Log: Merged from r215194:
[mips] Initial implementation of -mabicalls/-mno-abicalls. This patch implements the main rules for -mno-abicalls such as reserving $gp, and emitting the correct .option directive. Patch by Matheus Almeida and Toma Tabacu Differential Revision: http://reviews.llvm.org/D4231 Modified: llvm/branches/release_35/lib/Target/Mips/Mips.td llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp llvm/branches/release_35/lib/Target/Mips/MipsRegisterInfo.cpp llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.cpp llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h Modified: llvm/branches/release_35/lib/Target/Mips/Mips.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/Mips.td?rev=223009&r1=223008&r2=223009&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/Mips.td (original) +++ llvm/branches/release_35/lib/Target/Mips/Mips.td Mon Dec 1 05:32:07 2014 @@ -57,6 +57,8 @@ def MipsInstrInfo : InstrInfo; // Mips Subtarget features // //===----------------------------------------------------------------------===// +def FeatureABICalls : SubtargetFeature<"abicalls", "IsABICalls", "true", + "SVR4-style position-independent code.">; def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", "General Purpose Registers are 64-bit wide.">; def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", Modified: llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp?rev=223009&r1=223008&r2=223009&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp Mon Dec 1 05:32:07 2014 @@ -667,9 +667,7 @@ printFCCOperand(const MachineInstr *MI, } void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { - // TODO: Need to add -mabicalls and -mno-abicalls flags. - // Currently we assume that -mabicalls is the default. - bool IsABICalls = true; + bool IsABICalls = Subtarget->isABICalls(); if (IsABICalls) { getTargetStreamer().emitDirectiveAbiCalls(); Reloc::Model RM = TM.getRelocationModel(); Modified: llvm/branches/release_35/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsRegisterInfo.cpp?rev=223009&r1=223008&r2=223009&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsRegisterInfo.cpp Mon Dec 1 05:32:07 2014 @@ -149,6 +149,12 @@ getReservedRegs(const MachineFunction &M for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I) Reserved.set(ReservedGPR64[I]); + // For mno-abicalls, GP is a program invariant! + if (!Subtarget.isABICalls()) { + Reserved.set(Mips::GP); + Reserved.set(Mips::GP_64); + } + if (Subtarget.isFP64bit()) { // Reserve all registers in AFGR64. for (RegIter Reg = Mips::AFGR64RegClass.begin(), Modified: llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.cpp?rev=223009&r1=223008&r2=223009&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.cpp (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.cpp Mon Dec 1 05:32:07 2014 @@ -107,12 +107,13 @@ MipsSubtarget::MipsSubtarget(const std:: MipsTargetMachine *_TM) : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32), MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false), - IsFPXX(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false), - IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsLinux(true), - HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), - HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), - InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), - HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), + IsFPXX(false), IsABICalls(true), IsFP64bit(false), UseOddSPReg(true), + IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), + IsLinux(true), HasMips3_32(false), HasMips3_32r2(false), + HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false), + InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), + InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), + AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), TM(_TM), TargetTriple(TT), DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))), TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*this)), Modified: llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h?rev=223009&r1=223008&r2=223009&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h Mon Dec 1 05:32:07 2014 @@ -65,6 +65,9 @@ protected: // IsFPXX - MIPS O32 modeless ABI. bool IsFPXX; + // IsABICalls - SVR4-style position-independent code. + bool IsABICalls; + // IsFP64bit - The target processor has 64-bit floating point registers. bool IsFP64bit; @@ -200,6 +203,7 @@ public: bool hasCnMips() const { return HasCnMips; } bool isLittle() const { return IsLittle; } + bool isABICalls() const { return IsABICalls; } bool isFPXX() const { return IsFPXX; } bool isFP64bit() const { return IsFP64bit; } bool useOddSPReg() const { return UseOddSPReg; } _______________________________________________ llvm-branch-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
