Author: dsanders Date: Mon Dec 1 07:15:04 2014 New Revision: 223013 URL: http://llvm.org/viewvc/llvm-project?rev=223013&view=rev Log: Merged from r217434:
[mips] Don't cache IsO32 and IsFP64 in MipsTargetLowering::MipsCC Summary: Use a MipsSubtarget reference instead. No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5008 Modified: llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h Modified: llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp?rev=223013&r1=223012&r2=223013&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp Mon Dec 1 07:15:04 2014 @@ -2476,8 +2476,7 @@ MipsTargetLowering::LowerCall(TargetLowe getTargetMachine(), ArgLocs, *DAG.getContext()); MipsCC::SpecialCallingConvType SpecialCallingConv = getSpecialCallingConv(Callee); - MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(), - CCInfo, SpecialCallingConv); + MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo, SpecialCallingConv); MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, Subtarget.abiUsesSoftFloat(), @@ -2678,8 +2677,7 @@ MipsTargetLowering::LowerCallResult(SDVa SmallVector<CCValAssign, 16> RVLocs; CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), getTargetMachine(), RVLocs, *DAG.getContext()); - MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(), - CCInfo); + MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo); MipsCCInfo.analyzeCallResult(Ins, Subtarget.abiUsesSoftFloat(), CallNode, RetTy); @@ -2726,8 +2724,7 @@ MipsTargetLowering::LowerFormalArguments SmallVector<CCValAssign, 16> ArgLocs; CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), getTargetMachine(), ArgLocs, *DAG.getContext()); - MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(), - CCInfo); + MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo); Function::const_arg_iterator FuncArg = DAG.getMachineFunction().getFunction()->arg_begin(); bool UseSoftFloat = Subtarget.abiUsesSoftFloat(); @@ -2879,8 +2876,7 @@ MipsTargetLowering::LowerReturn(SDValue // CCState - Info about the registers and stack slot. CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs, *DAG.getContext()); - MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(), - CCInfo); + MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo); // Analyze return values. MipsCCInfo.analyzeReturn(Outs, Subtarget.abiUsesSoftFloat(), @@ -3389,10 +3385,10 @@ MipsTargetLowering::MipsCC::SpecialCalli } MipsTargetLowering::MipsCC::MipsCC( - CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info, - MipsCC::SpecialCallingConvType SpecialCallingConv_) - : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_), - SpecialCallingConv(SpecialCallingConv_){ + CallingConv::ID CC, const MipsSubtarget &Subtarget_, CCState &Info, + MipsCC::SpecialCallingConvType SpecialCallingConv_) + : CCInfo(Info), CallConv(CC), Subtarget(Subtarget_), + SpecialCallingConv(SpecialCallingConv_) { // Pre-allocate reserved argument area. CCInfo.AllocateStack(reservedArgArea(), 1); } @@ -3529,15 +3525,16 @@ void MipsTargetLowering::MipsCC::handleB } unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const { - return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs); + return Subtarget.isABI_O32() ? array_lengthof(O32IntRegs) + : array_lengthof(Mips64IntRegs); } unsigned MipsTargetLowering::MipsCC::reservedArgArea() const { - return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0; + return (Subtarget.isABI_O32() && (CallConv != CallingConv::Fast)) ? 16 : 0; } const MCPhysReg *MipsTargetLowering::MipsCC::intArgRegs() const { - return IsO32 ? O32IntRegs : Mips64IntRegs; + return Subtarget.isABI_O32() ? O32IntRegs : Mips64IntRegs; } llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const { @@ -3546,15 +3543,19 @@ llvm::CCAssignFn *MipsTargetLowering::Mi if (SpecialCallingConv == Mips16RetHelperConv) return CC_Mips16RetHelper; - return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN; + return Subtarget.isABI_O32() + ? (Subtarget.isFP64bit() ? CC_MipsO32_FP64 : CC_MipsO32_FP32) + : CC_MipsN; } llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const { - return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg; + return Subtarget.isABI_O32() + ? (Subtarget.isFP64bit() ? CC_MipsO32_FP64 : CC_MipsO32_FP32) + : CC_MipsN_VarArg; } const MCPhysReg *MipsTargetLowering::MipsCC::shadowRegs() const { - return IsO32 ? O32IntRegs : Mips64DPRegs; + return Subtarget.isABI_O32() ? O32IntRegs : Mips64DPRegs; } void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, @@ -3583,7 +3584,7 @@ void MipsTargetLowering::MipsCC::allocat MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode, bool IsSoftFloat) const { - if (IsSoftFloat || IsO32) + if (IsSoftFloat || Subtarget.isABI_O32()) return VT; // Check if the original type was fp128. @@ -3595,6 +3596,10 @@ MVT MipsTargetLowering::MipsCC::getRegVT return VT; } +unsigned MipsTargetLowering::MipsCC::regSize() const { + return Subtarget.isGP32bit() ? 4 : 8; +} + void MipsTargetLowering:: copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, Modified: llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h?rev=223013&r1=223012&r2=223013&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h Mon Dec 1 07:15:04 2014 @@ -355,10 +355,10 @@ namespace llvm { Mips16RetHelperConv, NoSpecialCallingConv }; - MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info, + MipsCC(CallingConv::ID CallConv, const MipsSubtarget &Subtarget, + CCState &Info, SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv); - void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, @@ -380,7 +380,7 @@ namespace llvm { bool hasByValArg() const { return !ByValArgs.empty(); } /// regSize - Size (in number of bits) of integer registers. - unsigned regSize() const { return IsO32 ? 4 : 8; } + unsigned regSize() const; /// numIntArgRegs - Number of integer registers available for calls. unsigned numIntArgRegs() const; @@ -429,7 +429,7 @@ namespace llvm { CCState &CCInfo; CallingConv::ID CallConv; - bool IsO32, IsFP64; + const MipsSubtarget &Subtarget; SpecialCallingConvType SpecialCallingConv; SmallVector<ByValArgInfo, 2> ByValArgs; }; _______________________________________________ llvm-branch-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
