Author: dsanders Date: Mon Dec 1 08:30:22 2014 New Revision: 223027 URL: http://llvm.org/viewvc/llvm-project?rev=223027&view=rev Log: Merged from r220568:
[mips] Replace MipsABIEnum with a MipsABIInfo class. Summary: No functional change yet, it's just an object replacement for an enum. It will allow us to gather ABI information in a single place so that we can start testing for properties of the ABI's instead of the ABI itself. For example we will eventually be able to use: ABI.MinStackAlignmentInBytes() instead of: (isABI_N32() || isABI_N64()) ? 16 : 8 which is clearer and more maintainable. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3341 Modified: llvm/branches/release_35/lib/Target/Mips/Mips.td llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp llvm/branches/release_35/lib/Target/Mips/MipsConstantIslandPass.cpp llvm/branches/release_35/lib/Target/Mips/MipsLongBranch.cpp llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.cpp llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h Modified: llvm/branches/release_35/lib/Target/Mips/Mips.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/Mips.td?rev=223027&r1=223026&r2=223027&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/Mips.td (original) +++ llvm/branches/release_35/lib/Target/Mips/Mips.td Mon Dec 1 08:30:22 2014 @@ -69,13 +69,13 @@ def FeatureNaN2008 : SubtargetFeatur "IEEE 754-2008 NaN encoding.">; def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", "true", "Only supports single precision float">; -def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", +def FeatureO32 : SubtargetFeature<"o32", "ABI", "MipsABIInfo::O32()", "Enable o32 ABI">; -def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32", +def FeatureN32 : SubtargetFeature<"n32", "ABI", "MipsABIInfo::N32()", "Enable n32 ABI">; -def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64", +def FeatureN64 : SubtargetFeature<"n64", "ABI", "MipsABIInfo::N64()", "Enable n64 ABI">; -def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", +def FeatureEABI : SubtargetFeature<"eabi", "ABI", "MipsABIInfo::EABI()", "Enable eabi ABI">; def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false", "Disable odd numbered single-precision " Modified: llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp?rev=223027&r1=223026&r2=223027&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp Mon Dec 1 08:30:22 2014 @@ -317,11 +317,11 @@ void MipsAsmPrinter::emitFrameDirective( /// Emit Set directives. const char *MipsAsmPrinter::getCurrentABIString() const { - switch (Subtarget->getTargetABI()) { - case MipsSubtarget::O32: return "abi32"; - case MipsSubtarget::N32: return "abiN32"; - case MipsSubtarget::N64: return "abi64"; - case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64 + switch (Subtarget->getABI().GetEnumValue()) { + case MipsABIInfo::ABI::O32: return "abi32"; + case MipsABIInfo::ABI::N32: return "abiN32"; + case MipsABIInfo::ABI::N64: return "abi64"; + case MipsABIInfo::ABI::EABI: return "eabi32"; // TODO: handle eabi64 default: llvm_unreachable("Unknown Mips ABI"); } } Modified: llvm/branches/release_35/lib/Target/Mips/MipsConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsConstantIslandPass.cpp?rev=223027&r1=223026&r2=223027&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsConstantIslandPass.cpp (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsConstantIslandPass.cpp Mon Dec 1 08:30:22 2014 @@ -343,7 +343,6 @@ namespace { const TargetMachine &TM; bool IsPIC; - unsigned ABI; const MipsSubtarget *STI; const Mips16InstrInfo *TII; MipsFunctionInfo *MFI; @@ -366,8 +365,7 @@ namespace { static char ID; MipsConstantIslands(TargetMachine &tm) : MachineFunctionPass(ID), TM(tm), - IsPIC(TM.getRelocationModel() == Reloc::PIC_), - ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()), STI(nullptr), + IsPIC(TM.getRelocationModel() == Reloc::PIC_), STI(nullptr), MF(nullptr), MCP(nullptr), PrescannedForConstants(false) {} const char *getPassName() const override { Modified: llvm/branches/release_35/lib/Target/Mips/MipsLongBranch.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsLongBranch.cpp?rev=223027&r1=223026&r2=223027&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsLongBranch.cpp (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsLongBranch.cpp Mon Dec 1 08:30:22 2014 @@ -64,8 +64,8 @@ namespace { MipsLongBranch(TargetMachine &tm) : MachineFunctionPass(ID), TM(tm), IsPIC(TM.getRelocationModel() == Reloc::PIC_), - ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()), - LongBranchSeqSize(!IsPIC ? 2 : (ABI == MipsSubtarget::N64 ? 10 : + ABI(TM.getSubtarget<MipsSubtarget>().getABI()), + LongBranchSeqSize(!IsPIC ? 2 : (ABI.IsN64() ? 10 : (!TM.getSubtarget<MipsSubtarget>().isTargetNaCl() ? 9 : 10))) {} const char *getPassName() const override { @@ -86,7 +86,7 @@ namespace { MachineFunction *MF; SmallVector<MBBInfo, 16> MBBInfos; bool IsPIC; - unsigned ABI; + MipsABIInfo ABI; unsigned LongBranchSeqSize; }; @@ -273,7 +273,7 @@ void MipsLongBranch::expandToLongBranch( const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>(); unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR; - if (ABI != MipsSubtarget::N64) { + if (!ABI.IsN64()) { // $longbr: // addiu $sp, $sp, -8 // sw $ra, 0($sp) Modified: llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.cpp?rev=223027&r1=223026&r2=223027&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.cpp (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.cpp Mon Dec 1 08:30:22 2014 @@ -106,7 +106,7 @@ MipsSubtarget::MipsSubtarget(const std:: const std::string &FS, bool little, MipsTargetMachine *_TM) : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32), - MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false), + ABI(MipsABIInfo::Unknown()), IsLittle(little), IsSingleFloat(false), IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsLinux(true), HasMips3_32(false), HasMips3_32r2(false), @@ -136,7 +136,7 @@ MipsSubtarget::MipsSubtarget(const std:: report_fatal_error("Code generation for MIPS-V is not implemented", false); // Assert exactly one ABI was chosen. - assert(MipsABI != UnknownABI); + assert(ABI.IsKnown()); assert((((getFeatureBits() & Mips::FeatureO32) != 0) + ((getFeatureBits() & Mips::FeatureEABI) != 0) + ((getFeatureBits() & Mips::FeatureN32) != 0) + Modified: llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h?rev=223027&r1=223026&r2=223027&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h Mon Dec 1 08:30:22 2014 @@ -23,6 +23,7 @@ #include "llvm/MC/MCInstrItineraries.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetSubtargetInfo.h" +#include "MipsABIInfo.h" #include <string> #define GET_SUBTARGETINFO_HEADER @@ -36,13 +37,6 @@ class MipsTargetMachine; class MipsSubtarget : public MipsGenSubtargetInfo { virtual void anchor(); -public: - // NOTE: O64 will not be supported. - enum MipsABIEnum { - UnknownABI, O32, N32, N64, EABI - }; - -protected: enum MipsArchEnum { Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r6 @@ -51,8 +45,8 @@ protected: // Mips architecture version MipsArchEnum MipsArchVersion; - // Mips supported ABIs - MipsABIEnum MipsABI; + // Selected ABI + MipsABIInfo ABI; // IsLittle - The target is Little Endian bool IsLittle; @@ -160,12 +154,12 @@ public: CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override; /// Only O32 and EABI supported right now. - bool isABI_EABI() const { return MipsABI == EABI; } - bool isABI_N64() const { return MipsABI == N64; } - bool isABI_N32() const { return MipsABI == N32; } - bool isABI_O32() const { return MipsABI == O32; } + bool isABI_EABI() const { return ABI.IsEABI(); } + bool isABI_N64() const { return ABI.IsN64(); } + bool isABI_N32() const { return ABI.IsN32(); } + bool isABI_O32() const { return ABI.IsO32(); } bool isABI_FPXX() const { return isABI_O32() && IsFPXX; } - unsigned getTargetABI() const { return MipsABI; } + const MipsABIInfo &getABI() const { return ABI; } /// This constructor initializes the data members to match that /// of the specified triple. _______________________________________________ llvm-branch-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
