Author: dsanders Date: Fri Mar 6 06:34:10 2015 New Revision: 231466 URL: http://llvm.org/viewvc/llvm-project?rev=231466&view=rev Log: Merging r225529: ------------------------------------------------------------------------ r225529 | dsanders | 2015-01-09 17:21:30 +0000 (Fri, 09 Jan 2015) | 18 lines
[mips] Add support for accessing $gp as a named register. Summary: Mips Linux uses $gp to hold a pointer to thread info structure and accesses it with a named register. This makes this work for LLVM. The N32 ABI doesn't quite work yet since the frontend generates incorrect IR for this case. It neglects to truncate the 64-bit GPR to a 32-bit value before converting to a pointer. Given correct IR (as in the testcase in this patch), it works correctly. Reviewers: sstankovic, vmedic, atanasyan Reviewed By: atanasyan Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6893 ------------------------------------------------------------------------ Added: llvm/branches/release_35/test/CodeGen/Mips/named-register-n32.ll llvm/branches/release_35/test/CodeGen/Mips/named-register-n64.ll llvm/branches/release_35/test/CodeGen/Mips/named-register-o32.ll Modified: llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h Modified: llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp?rev=231466&r1=231465&r2=231466&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp Fri Mar 6 06:34:10 2015 @@ -3721,3 +3721,25 @@ void MipsTargetLowering::HandleByVal(CCS State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); } + +// FIXME? Maybe this could be a TableGen attribute on some registers and +// this table could be generated automatically from RegInfo. +unsigned MipsTargetLowering::getRegisterByName(const char* RegName, + EVT VT) const { + // Named registers is expected to be fairly rare. For now, just support $28 + // since the linux kernel uses it. + if (Subtarget.isGP64bit()) { + unsigned Reg = StringSwitch<unsigned>(RegName) + .Case("$28", Mips::GP_64) + .Default(0); + if (Reg) + return Reg; + } else { + unsigned Reg = StringSwitch<unsigned>(RegName) + .Case("$28", Mips::GP) + .Default(0); + if (Reg) + return Reg; + } + report_fatal_error("Invalid register name global variable"); +} Modified: llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h?rev=231466&r1=231465&r2=231466&view=diff ============================================================================== --- llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h Fri Mar 6 06:34:10 2015 @@ -262,6 +262,8 @@ namespace llvm { void HandleByVal(CCState *, unsigned &, unsigned) const override; + unsigned getRegisterByName(const char* RegName, EVT VT) const override; + protected: SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; Added: llvm/branches/release_35/test/CodeGen/Mips/named-register-n32.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/named-register-n32.ll?rev=231466&view=auto ============================================================================== --- llvm/branches/release_35/test/CodeGen/Mips/named-register-n32.ll (added) +++ llvm/branches/release_35/test/CodeGen/Mips/named-register-n32.ll Fri Mar 6 06:34:10 2015 @@ -0,0 +1,18 @@ +; RUN: llc -march=mips64 -relocation-model=static -mattr=+noabicalls,-n64,+n32 < %s | FileCheck %s + +define i32* @get_gp() { +entry: + %0 = call i64 @llvm.read_register.i64(metadata !0) + %1 = trunc i64 %0 to i32 + %2 = inttoptr i32 %1 to i32* + ret i32* %2 +} + +; CHECK-LABEL: get_gp: +; CHECK: sll $2, $gp, 0 + +declare i64 @llvm.read_register.i64(metadata) + +!llvm.named.register.$28 = !{!0} + +!0 = metadata !{metadata !"$28"} Added: llvm/branches/release_35/test/CodeGen/Mips/named-register-n64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/named-register-n64.ll?rev=231466&view=auto ============================================================================== --- llvm/branches/release_35/test/CodeGen/Mips/named-register-n64.ll (added) +++ llvm/branches/release_35/test/CodeGen/Mips/named-register-n64.ll Fri Mar 6 06:34:10 2015 @@ -0,0 +1,17 @@ +; RUN: llc -march=mips64 -relocation-model=static -mattr=+noabicalls < %s | FileCheck %s + +define i32* @get_gp() { +entry: + %0 = call i64 @llvm.read_register.i64(metadata !0) + %1 = inttoptr i64 %0 to i32* + ret i32* %1 +} + +; CHECK-LABEL: get_gp: +; CHECK: move $2, $gp + +declare i64 @llvm.read_register.i64(metadata) + +!llvm.named.register.$28 = !{!0} + +!0 = metadata !{metadata !"$28"} Added: llvm/branches/release_35/test/CodeGen/Mips/named-register-o32.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/named-register-o32.ll?rev=231466&view=auto ============================================================================== --- llvm/branches/release_35/test/CodeGen/Mips/named-register-o32.ll (added) +++ llvm/branches/release_35/test/CodeGen/Mips/named-register-o32.ll Fri Mar 6 06:34:10 2015 @@ -0,0 +1,17 @@ +; RUN: llc -march=mips -relocation-model=static -mattr=+noabicalls < %s | FileCheck %s + +define i32* @get_gp() { +entry: + %0 = call i32 @llvm.read_register.i32(metadata !0) + %1 = inttoptr i32 %0 to i32* + ret i32* %1 +} + +; CHECK-LABEL: get_gp: +; CHECK: move $2, $gp + +declare i32 @llvm.read_register.i32(metadata) + +!llvm.named.register.$28 = !{!0} + +!0 = metadata !{metadata !"$28"} _______________________________________________ llvm-branch-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
