Author: tstellar Date: Fri Apr 17 11:59:33 2015 New Revision: 235208 URL: http://llvm.org/viewvc/llvm-project?rev=235208&view=rev Log: Merging r227987:
------------------------------------------------------------------------ r227987 | marek.olsak | 2015-02-03 12:37:57 -0500 (Tue, 03 Feb 2015) | 12 lines R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2 These are VOP2 on SI and VOP3 on VI, and their pseudos are neither, which can be a problem. In order to make isVOP2 and isVOP3 queries behave as expected, the encoding must be determined first. This doesn't fix any known issue, but better safe than sorry. v2: add and use getMCOpcodeFromPseudo Tested-by: Michel Dänzer <[email protected]> ------------------------------------------------------------------------ Modified: llvm/branches/release_36/lib/Target/R600/AMDGPUInstrInfo.h llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp Modified: llvm/branches/release_36/lib/Target/R600/AMDGPUInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/AMDGPUInstrInfo.h?rev=235208&r1=235207&r2=235208&view=diff ============================================================================== --- llvm/branches/release_36/lib/Target/R600/AMDGPUInstrInfo.h (original) +++ llvm/branches/release_36/lib/Target/R600/AMDGPUInstrInfo.h Fri Apr 17 11:59:33 2015 @@ -140,6 +140,12 @@ public: /// not exist. If Opcode is not a pseudo instruction, this is identity. int pseudoToMCOpcode(int Opcode) const; + /// \brief Return the descriptor of the target-specific machine instruction + /// that corresponds to the specified pseudo or native opcode. + const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const { + return get(pseudoToMCOpcode(Opcode)); + } + //===---------------------------------------------------------------------===// // Pure virtual funtions to be implemented by sub-classes. //===---------------------------------------------------------------------===// Modified: llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp?rev=235208&r1=235207&r2=235208&view=diff ============================================================================== --- llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp (original) +++ llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.cpp Fri Apr 17 11:59:33 2015 @@ -204,7 +204,9 @@ void SIRegisterInfo::eliminateFrameIndex Ctx.emitError("Ran out of VGPRs for spilling SGPR"); } - BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill.VGPR) + BuildMI(*MBB, MI, DL, + TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32), + Spill.VGPR) .addReg(SubReg) .addImm(Spill.Lane); @@ -236,7 +238,9 @@ void SIRegisterInfo::eliminateFrameIndex if (isM0) SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0); - BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg) + BuildMI(*MBB, MI, DL, + TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), + SubReg) .addReg(Spill.VGPR) .addImm(Spill.Lane) .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); _______________________________________________ llvm-branch-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
