Author: tstellar Date: Mon Apr 20 13:06:09 2015 New Revision: 235316 URL: http://llvm.org/viewvc/llvm-project?rev=235316&view=rev Log: Merging r227989:
------------------------------------------------------------------------ r227989 | marek.olsak | 2015-02-03 12:38:05 -0500 (Tue, 03 Feb 2015) | 10 lines R600/SI: Remove VOP2_REV definitions from target-specific instructions The getCommute* functions are only used with pseudos, so this commit doesn't change anything. The issue with missing non-rev versions of shift instructions on VI will fixed separately. Tested-by: Michel Dänzer <[email protected]> ------------------------------------------------------------------------ Modified: llvm/branches/release_36/lib/Target/R600/SIInstrInfo.td llvm/branches/release_36/lib/Target/R600/SIInstructions.td Modified: llvm/branches/release_36/lib/Target/R600/SIInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIInstrInfo.td?rev=235316&r1=235315&r2=235316&view=diff ============================================================================== --- llvm/branches/release_36/lib/Target/R600/SIInstrInfo.td (original) +++ llvm/branches/release_36/lib/Target/R600/SIInstrInfo.td Mon Apr 20 13:06:09 2015 @@ -850,25 +850,22 @@ class VOP2_Pseudo <dag outs, dag ins, li } multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern, - string opName, string revOpSI> { + string opName, string revOp> { def "" : VOP2_Pseudo <outs, ins, pattern, opName>, - VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>; + VOP2_REV<revOp#"_e32", !eq(revOp, opName)>; def _si : VOP2 <op.SI, outs, ins, opName#asm, []>, - VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>, SIMCInstr <opName#"_e32", SISubtarget.SI>; } multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern, - string opName, string revOpSI, string revOpVI> { + string opName, string revOp> { def "" : VOP2_Pseudo <outs, ins, pattern, opName>, - VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>; + VOP2_REV<revOp#"_e32", !eq(revOp, opName)>; def _si : VOP2 <op.SI, outs, ins, opName#asm, []>, - VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>, SIMCInstr <opName#"_e32", SISubtarget.SI>; def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>, - VOP2_REV<revOpVI#"_e32_vi", !eq(revOpVI, opName)>, SIMCInstr <opName#"_e32", SISubtarget.VI>; } @@ -942,20 +939,18 @@ multiclass VOP3_1_m <vop op, dag outs, d } multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm, - list<dag> pattern, string opName, string revOpSI, string revOpVI, + list<dag> pattern, string opName, string revOp, bit HasMods = 1, bit UseFullOp = 0> { def "" : VOP3_Pseudo <outs, ins, pattern, opName>, - VOP2_REV<revOpSI#"_e64", !eq(revOpSI, opName)>; + VOP2_REV<revOp#"_e64", !eq(revOp, opName)>; def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, - VOP2_REV<revOpSI#"_e64_si", !eq(revOpSI, opName)>, VOP3DisableFields<1, 0, HasMods>; def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>, - VOP2_REV<revOpVI#"_e64_vi", !eq(revOpVI, opName)>, VOP3DisableFields<1, 0, HasMods>; } @@ -971,14 +966,12 @@ multiclass VOP3b_2_m <vop op, dag outs, let sdst = SIOperand.VCC, Defs = [VCC] in { def _si : VOP3b <op.SI3, outs, ins, asm, []>, VOP3DisableFields<1, 0, HasMods>, - SIMCInstr<opName#"_e64", SISubtarget.SI>, - VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>; + SIMCInstr<opName#"_e64", SISubtarget.SI>; // TODO: Do we need this VI variant here? /*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, []>, VOP3DisableFields<1, 0, HasMods>, - SIMCInstr<opName#"_e64", SISubtarget.VI>, - VOP2_REV<revOp#"_e64_vi", !eq(revOp, opName)>;*/ + SIMCInstr<opName#"_e64", SISubtarget.VI>;*/ } // End sdst = SIOperand.VCC, Defs = [VCC] } @@ -1057,17 +1050,17 @@ multiclass VOP1InstSI <vop1 op, string o multiclass VOP2_Helper <vop2 op, string opName, dag outs, dag ins32, string asm32, list<dag> pat32, dag ins64, string asm64, list<dag> pat64, - string revOpSI, string revOpVI, bit HasMods> { - defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOpSI, revOpVI>; + string revOp, bit HasMods> { + defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>; defm _e64 : VOP3_2_m <op, - outs, ins64, opName#"_e64"#asm64, pat64, opName, revOpSI, revOpVI, HasMods + outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods >; } multiclass VOP2Inst <vop2 op, string opName, VOPProfile P, SDPatternOperator node = null_frag, - string revOpSI = opName, string revOpVI = revOpSI> : VOP2_Helper < + string revOp = opName> : VOP2_Helper < op, opName, P.Outs, P.Ins32, P.Asm32, [], P.Ins64, P.Asm64, @@ -1077,7 +1070,7 @@ multiclass VOP2Inst <vop2 op, string opN i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), - revOpSI, revOpVI, P.HasModifiers + revOp, P.HasModifiers >; multiclass VOP2b_Helper <vop2 op, string opName, dag outs, @@ -1085,7 +1078,7 @@ multiclass VOP2b_Helper <vop2 op, string dag ins64, string asm64, list<dag> pat64, string revOp, bit HasMods> { - defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp, revOp>; + defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>; defm _e64 : VOP3b_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods @@ -1111,16 +1104,16 @@ multiclass VOP2bInst <vop2 op, string op multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs, dag ins32, string asm32, list<dag> pat32, dag ins64, string asm64, list<dag> pat64, - string revOpSI, string revOpVI, bit HasMods> { - defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOpSI>; + string revOp, bit HasMods> { + defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>; defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, - revOpSI, revOpVI, HasMods>; + revOp, HasMods>; } multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P, SDPatternOperator node = null_frag, - string revOpSI = opName, string revOpVI = revOpSI> + string revOp = opName> : VOP2_VI3_Helper < op, opName, P.Outs, P.Ins32, P.Asm32, [], @@ -1131,7 +1124,7 @@ multiclass VOP2_VI3_Inst <vop23 op, stri i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), - revOpSI, revOpVI, P.HasModifiers + revOp, P.HasModifiers >; class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> : Modified: llvm/branches/release_36/lib/Target/R600/SIInstructions.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIInstructions.td?rev=235316&r1=235315&r2=235316&view=diff ============================================================================== --- llvm/branches/release_36/lib/Target/R600/SIInstructions.td (original) +++ llvm/branches/release_36/lib/Target/R600/SIInstructions.td Mon Apr 20 13:06:09 2015 @@ -1455,22 +1455,19 @@ defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0x AMDGPUumax >; -// No non-Rev Op on VI defm V_LSHRREV_B32 : VOP2Inst < vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag, - "v_lshr_b32", "v_lshrrev_b32" + "v_lshr_b32" >; -// No non-Rev OP on VI defm V_ASHRREV_I32 : VOP2Inst < vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag, - "v_ashr_i32", "v_ashrrev_i32" + "v_ashr_i32" >; -// No non-Rev OP on VI defm V_LSHLREV_B32 : VOP2Inst < vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag, - "v_lshl_b32", "v_lshlrev_b32" + "v_lshl_b32" >; defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", _______________________________________________ llvm-branch-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
