Author: hans Date: Thu Jul 23 12:50:15 2015 New Revision: 243027 URL: http://llvm.org/viewvc/llvm-project?rev=243027&view=rev Log: Merging r243001: ------------------------------------------------------------------------ r243001 | mkuper | 2015-07-23 03:23:48 -0700 (Thu, 23 Jul 2015) | 4 lines
[X86] Fix order of operands for ins and outs instructions when parsing intel syntax Patch by: [email protected] Differential Revision: http://reviews.llvm.org/D11337 ------------------------------------------------------------------------ Modified: llvm/branches/release_37/ (props changed) llvm/branches/release_37/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/branches/release_37/test/MC/X86/intel-syntax.s Propchange: llvm/branches/release_37/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Thu Jul 23 12:50:15 2015 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993 +/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001 Modified: llvm/branches/release_37/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=243027&r1=243026&r2=243027&view=diff ============================================================================== --- llvm/branches/release_37/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/branches/release_37/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Jul 23 12:50:15 2015 @@ -681,6 +681,9 @@ private: std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc); std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc); + void AddDefaultSrcDestOperands( + OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src, + std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst); std::unique_ptr<X86Operand> ParseOperand(); std::unique_ptr<X86Operand> ParseATTOperand(); std::unique_ptr<X86Operand> ParseIntelOperand(); @@ -1014,6 +1017,19 @@ std::unique_ptr<X86Operand> X86AsmParser Loc, Loc, 0); } +void X86AsmParser::AddDefaultSrcDestOperands( + OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src, + std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) { + if (isParsingIntelSyntax()) { + Operands.push_back(std::move(Dst)); + Operands.push_back(std::move(Src)); + } + else { + Operands.push_back(std::move(Src)); + Operands.push_back(std::move(Dst)); + } +} + std::unique_ptr<X86Operand> X86AsmParser::ParseOperand() { if (isParsingIntelSyntax()) return ParseIntelOperand(); @@ -2228,26 +2244,18 @@ bool X86AsmParser::ParseInstruction(Pars if (Name.startswith("ins") && Operands.size() == 1 && (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" )) { - if (isParsingIntelSyntax()) { - Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc)); - Operands.push_back(DefaultMemDIOperand(NameLoc)); - } else { - Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc)); - Operands.push_back(DefaultMemDIOperand(NameLoc)); - } + AddDefaultSrcDestOperands(Operands, + X86Operand::CreateReg(X86::DX, NameLoc, NameLoc), + DefaultMemDIOperand(NameLoc)); } // Append default arguments to "outs[bwld]" if (Name.startswith("outs") && Operands.size() == 1 && (Name == "outsb" || Name == "outsw" || Name == "outsl" || Name == "outsd" )) { - if (isParsingIntelSyntax()) { - Operands.push_back(DefaultMemSIOperand(NameLoc)); - Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc)); - } else { - Operands.push_back(DefaultMemSIOperand(NameLoc)); - Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc)); - } + AddDefaultSrcDestOperands(Operands, + DefaultMemSIOperand(NameLoc), + X86Operand::CreateReg(X86::DX, NameLoc, NameLoc)); } // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate @@ -2279,13 +2287,9 @@ bool X86AsmParser::ParseInstruction(Pars (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" || Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) { if (Operands.size() == 1) { - if (isParsingIntelSyntax()) { - Operands.push_back(DefaultMemSIOperand(NameLoc)); - Operands.push_back(DefaultMemDIOperand(NameLoc)); - } else { - Operands.push_back(DefaultMemDIOperand(NameLoc)); - Operands.push_back(DefaultMemSIOperand(NameLoc)); - } + AddDefaultSrcDestOperands(Operands, + DefaultMemDIOperand(NameLoc), + DefaultMemSIOperand(NameLoc)); } else if (Operands.size() == 3) { X86Operand &Op = (X86Operand &)*Operands[1]; X86Operand &Op2 = (X86Operand &)*Operands[2]; @@ -2305,13 +2309,9 @@ bool X86AsmParser::ParseInstruction(Pars if (Operands.size() == 1) { if (Name == "movsd") Operands.back() = X86Operand::CreateToken("movsl", NameLoc); - if (isParsingIntelSyntax()) { - Operands.push_back(DefaultMemDIOperand(NameLoc)); - Operands.push_back(DefaultMemSIOperand(NameLoc)); - } else { - Operands.push_back(DefaultMemSIOperand(NameLoc)); - Operands.push_back(DefaultMemDIOperand(NameLoc)); - } + AddDefaultSrcDestOperands(Operands, + DefaultMemSIOperand(NameLoc), + DefaultMemDIOperand(NameLoc)); } else if (Operands.size() == 3) { X86Operand &Op = (X86Operand &)*Operands[1]; X86Operand &Op2 = (X86Operand &)*Operands[2]; Modified: llvm/branches/release_37/test/MC/X86/intel-syntax.s URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/MC/X86/intel-syntax.s?rev=243027&r1=243026&r2=243027&view=diff ============================================================================== --- llvm/branches/release_37/test/MC/X86/intel-syntax.s (original) +++ llvm/branches/release_37/test/MC/X86/intel-syntax.s Thu Jul 23 12:50:15 2015 @@ -665,3 +665,17 @@ frstor dword ptr [eax] // CHECK: cmpnless %xmm1, %xmm0 cmpnless xmm0, xmm1 + +insb +insw +insd +// CHECK: insb %dx, %es:(%rdi) +// CHECK: insw %dx, %es:(%rdi) +// CHECK: insl %dx, %es:(%rdi) + +outsb +outsw +outsd +// CHECK: outsb (%rsi), %dx +// CHECK: outsw (%rsi), %dx +// CHECK: outsl (%rsi), %dx _______________________________________________ llvm-branch-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
