Author: hans Date: Thu Jul 30 11:18:53 2015 New Revision: 243650 URL: http://llvm.org/viewvc/llvm-project?rev=243650&view=rev Log: Merging r243638 and r243640: ------------------------------------------------------------------------ r243638 | vkalintiris | 2015-07-30 05:39:33 -0700 (Thu, 30 Jul 2015) | 12 lines
[mips][FastISel] Remove hidden mips-fast-isel option. Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r243640 | vkalintiris | 2015-07-30 06:13:09 -0700 (Thu, 30 Jul 2015) | 5 lines [mips] Fix out-of-date debug information in test file. Update the debug info in the check-lines because the change in r243638 introduced a constant initialization before the prologue's end as part of a register spill. ------------------------------------------------------------------------ Modified: llvm/branches/release_37/ (props changed) llvm/branches/release_37/lib/Target/Mips/MipsISelLowering.cpp llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/br1.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/bswap1.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/callabi.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/div1.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fastalloca.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpext.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpintconv.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fptrunc.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/icmpa.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstore2.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/logopm.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/memtest1.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/mul1.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/nullvoid.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/overflt.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/rem1.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/retabi.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/sel1.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/shftopm.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/shift.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestore.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestorei.ll llvm/branches/release_37/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll llvm/branches/release_37/test/DebugInfo/Mips/delay-slot.ll Propchange: llvm/branches/release_37/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Thu Jul 30 11:18:53 2015 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243116,243263,243294,243361,243469,243485,243500,243519,243531,243636 +/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243116,243263,243294,243361,243469,243485,243500,243519,243531,243636,243638,243640 Modified: llvm/branches/release_37/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/Mips/MipsISelLowering.cpp?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/branches/release_37/lib/Target/Mips/MipsISelLowering.cpp Thu Jul 30 11:18:53 2015 @@ -27,6 +27,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/FunctionLoweringInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/IR/CallingConv.h" @@ -53,11 +54,6 @@ NoZeroDivCheck("mno-check-zero-division" cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false)); -cl::opt<bool> -EnableMipsFastISel("mips-fast-isel", cl::Hidden, - cl::desc("Allow mips-fast-isel to be used"), - cl::init(false)); - static const MCPhysReg Mips64DPRegs[8] = { Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 @@ -461,7 +457,7 @@ const MipsTargetLowering *MipsTargetLowe FastISel * MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const { - if (!EnableMipsFastISel) + if (!funcInfo.MF->getTarget().Options.EnableFastISel) return TargetLowering::createFastISel(funcInfo, libInfo); return Mips::createFastISel(funcInfo, libInfo); } Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/br1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/br1.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/br1.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/br1.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @b = global i32 1, align 4 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/bswap1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/bswap1.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/bswap1.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/bswap1.ll Thu Jul 30 11:18:53 2015 @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=1 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R1 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=1 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R2 @a = global i16 -21829, align 2 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/callabi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/callabi.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/callabi.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/callabi.ll Thu Jul 30 11:18:53 2015 @@ -1,8 +1,8 @@ ; RUN: llc -march=mipsel -mcpu=mips32 -O0 \ -; RUN: -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \ +; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \ ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 ; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 \ -; RUN: -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \ +; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \ ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 declare void @xb(i8) Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll Thu Jul 30 11:18:53 2015 @@ -1,7 +1,7 @@ ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 < %s | FileCheck %s +; RUN: -fast-isel=true -fast-isel-abort=1 < %s | FileCheck %s ; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 < %s | FileCheck %s +; RUN: -fast-isel=true -fast-isel-abort=1 < %s | FileCheck %s @ARR = external global [10 x i32], align 4 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/div1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/div1.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/div1.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/div1.ll Thu Jul 30 11:18:53 2015 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel-abort=1 | FileCheck %s ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel-abort=1 | FileCheck %s @sj = global i32 200000, align 4 @sk = global i32 -47, align 4 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fastalloca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fastalloca.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fastalloca.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fastalloca.ll Thu Jul 30 11:18:53 2015 @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s %struct.x = type { i32 } Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-verbose 2>&1 | \ -; RUN: FileCheck %s +; RUN: -fast-isel-verbose 2>&1 | FileCheck %s ; CHECK: FastISel missed call: ; CHECK-SAME: %call = call fastcc i32 @foo(i32 signext %a, i32 signext %b) Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @f1 = common global float 0.000000e+00, align 4 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpext.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpext.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpext.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpext.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @f = global float 0x40147E6B80000000, align 4 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpintconv.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpintconv.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpintconv.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fpintconv.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fptrunc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fptrunc.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fptrunc.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/fptrunc.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @d = global double 0x40147E6B74DF0446, align 8 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/icmpa.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/icmpa.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/icmpa.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/icmpa.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @c = global i32 4, align 4 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstore2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstore2.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstore2.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstore2.ll Thu Jul 30 11:18:53 2015 @@ -4,9 +4,9 @@ target triple = "mips--linux-gnu" @c2 = common global i8 0, align 1 @c1 = common global i8 0, align 1 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @s2 = common global i16 0, align 2 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll Thu Jul 30 11:18:53 2015 @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32r2 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32 @b2 = global i8 0, align 1 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/logopm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/logopm.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/logopm.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/logopm.ll Thu Jul 30 11:18:53 2015 @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s @ub1 = common global i8 0, align 1 @ub2 = common global i8 0, align 1 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/memtest1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/memtest1.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/memtest1.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/memtest1.ll Thu Jul 30 11:18:53 2015 @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=1 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R1 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=1 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R2 @str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/mul1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/mul1.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/mul1.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/mul1.ll Thu Jul 30 11:18:53 2015 @@ -1,7 +1,5 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 \ -; RUN: -fast-isel -mips-fast-isel -relocation-model=pic -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 \ -; RUN: -fast-isel -mips-fast-isel -relocation-model=pic +; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic ; The test is just to make sure it is able to allocate ; registers for this example. There was an issue with allocating AC0 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/nullvoid.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/nullvoid.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/nullvoid.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/nullvoid.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s ; Function Attrs: nounwind Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/overflt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/overflt.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/overflt.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/overflt.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @x = common global [128000 x float] zeroinitializer, align 4 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/rem1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/rem1.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/rem1.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/rem1.ll Thu Jul 30 11:18:53 2015 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel-abort=1 | FileCheck %s ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel-abort=1 | FileCheck %s @sj = global i32 200, align 4 @sk = global i32 -47, align 4 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/retabi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/retabi.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/retabi.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/retabi.ll Thu Jul 30 11:18:53 2015 @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s @i = global i32 75, align 4 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/sel1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/sel1.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/sel1.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/sel1.ll Thu Jul 30 11:18:53 2015 @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O2 -relocation-model=pic \ -; RUN: -fast-isel -mips-fast-isel -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel -fast-isel-abort=1 | FileCheck %s define i1 @sel_i1(i1 %j, i1 %k, i1 %l) { entry: Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/shftopm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/shftopm.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/shftopm.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/shftopm.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 \ ; RUN: -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 \ ; RUN: -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s @s1 = global i16 -89, align 2 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/shift.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/shift.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/shift.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/shift.ll Thu Jul 30 11:18:53 2015 @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -O1 -fast-isel=true -mips-fast-isel -filetype=obj %s -o - \ +; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -fast-isel=true -filetype=obj %s -o - \ ; RUN: | llvm-objdump -arch mipsel -mcpu=mips32r2 -d - | FileCheck %s ; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used. Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestore.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestore.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestore.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestore.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @abcd = external global i32 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll Thu Jul 30 11:18:53 2015 @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32r2 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32 @f = common global float 0.000000e+00, align 4 Modified: llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestorei.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestorei.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestorei.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/Fast-ISel/simplestorei.ll Thu Jul 30 11:18:53 2015 @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @ijk = external global i32 Modified: llvm/branches/release_37/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll (original) +++ llvm/branches/release_37/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll Thu Jul 30 11:18:53 2015 @@ -1,10 +1,10 @@ ; Check that register scavenging spill slot is close to $fp. -; RUN: llc -march=mipsel -O0 < %s | FileCheck %s +; RUN: llc -march=mipsel -O0 -fast-isel=false < %s | FileCheck %s -; CHECK: sw ${{.*}}, 4($sp) -; CHECK: lw ${{.*}}, 4($sp) +; CHECK: sw ${{.*}}, 8($sp) +; CHECK: lw ${{.*}}, 8($sp) -define i32 @main(i32 signext %argc, i8** %argv) "no-frame-pointer-elim"="true" { +define i32 @main(i32 signext %argc, i8** %argv) #0 { entry: %retval = alloca i32, align 4 %argc.addr = alloca i32, align 4 @@ -30,3 +30,5 @@ entry: store <16 x i8> %mul, <16 x i8>* %result, align 16 ret i32 0 } + +attributes #0 = { noinline optnone "no-frame-pointer-elim"="true" } Modified: llvm/branches/release_37/test/DebugInfo/Mips/delay-slot.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/DebugInfo/Mips/delay-slot.ll?rev=243650&r1=243649&r2=243650&view=diff ============================================================================== --- llvm/branches/release_37/test/DebugInfo/Mips/delay-slot.ll (original) +++ llvm/branches/release_37/test/DebugInfo/Mips/delay-slot.ll Thu Jul 30 11:18:53 2015 @@ -13,12 +13,14 @@ ; CHECK: Address Line Column File ISA Discriminator Flags ; CHECK: ------------------ ------ ------ ------ --- ------------- ------------- ; CHECK: 0x0000000000000000 1 0 1 0 0 is_stmt -; CHECK: 0x0000000000000000 1 0 1 0 0 is_stmt prologue_end -; CHECK: 0x0000000000000008 2 0 1 0 0 is_stmt -; CHECK: 0x0000000000000020 3 0 1 0 0 is_stmt -; CHECK: 0x0000000000000030 4 0 1 0 0 is_stmt -; CHECK: 0x0000000000000040 5 0 1 0 0 is_stmt -; CHECK: 0x0000000000000050 5 0 1 0 0 is_stmt end_sequence +; FIXME: The next address probably ought to be 0x0000000000000004 but there's +; a constant initialization before the prologue's end. +; CHECK: 0x0000000000000008 2 0 1 0 0 is_stmt prologue_end +; CHECK: 0x0000000000000028 3 0 1 0 0 is_stmt +; CHECK: 0x0000000000000038 4 0 1 0 0 is_stmt +; CHECK: 0x0000000000000048 5 0 1 0 0 is_stmt +; CHECK: 0x0000000000000058 5 0 1 0 0 is_stmt end_sequence + target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64" target triple = "mips--linux-gnu" _______________________________________________ llvm-branch-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
