Author: Kerry McLaughlin Date: 2020-11-26T11:19:40Z New Revision: 4bee3197f665a8c2336a6cdd4bf5c4575b9e5fe7
URL: https://github.com/llvm/llvm-project/commit/4bee3197f665a8c2336a6cdd4bf5c4575b9e5fe7 DIFF: https://github.com/llvm/llvm-project/commit/4bee3197f665a8c2336a6cdd4bf5c4575b9e5fe7.diff LOG: [SVE][CodeGen] Extend isConstantSplatValue to support ISD::SPLAT_VECTOR Updated the affected scalable_of_scalable tests in sve-gep.ll, as isConstantSplatValue now returns true in DAGCombiner::visitMUL and folds `(mul x, 1) -> x` Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D91363 Added: Modified: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/test/CodeGen/AArch64/sve-gep.ll Removed: ################################################################################ diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index eee80cc4bc70..20e4ac590136 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -139,6 +139,15 @@ bool ConstantFPSDNode::isValueValidForType(EVT VT, //===----------------------------------------------------------------------===// bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) { + if (N->getOpcode() == ISD::SPLAT_VECTOR) { + unsigned EltSize = + N->getValueType(0).getVectorElementType().getSizeInBits(); + if (auto *Op0 = dyn_cast<ConstantSDNode>(N->getOperand(0))) { + SplatVal = Op0->getAPIntValue().truncOrSelf(EltSize); + return true; + } + } + auto *BV = dyn_cast<BuildVectorSDNode>(N); if (!BV) return false; diff --git a/llvm/test/CodeGen/AArch64/sve-gep.ll b/llvm/test/CodeGen/AArch64/sve-gep.ll index 8f68a38e2cd2..ffde9289a55d 100644 --- a/llvm/test/CodeGen/AArch64/sve-gep.ll +++ b/llvm/test/CodeGen/AArch64/sve-gep.ll @@ -105,11 +105,9 @@ define <vscale x 2 x <vscale x 2 x i64>*> @scalable_of_scalable_1(<vscale x 2 x ; CHECK-LABEL: scalable_of_scalable_1: ; CHECK: // %bb.0: ; CHECK-NEXT: rdvl x8, #1 -; CHECK-NEXT: mov z1.d, #1 // =0x1 -; CHECK-NEXT: mov z0.d, x0 -; CHECK-NEXT: mov z2.d, x8 -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: mla z0.d, p0/m, z2.d, z1.d +; CHECK-NEXT: mov z0.d, x8 +; CHECK-NEXT: mov z1.d, x0 +; CHECK-NEXT: add z0.d, z1.d, z0.d ; CHECK-NEXT: ret %idx = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer %d = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, <vscale x 2 x i64> %idx @@ -120,10 +118,8 @@ define <vscale x 2 x <vscale x 2 x i64>*> @scalable_of_scalable_2(<vscale x 2 x ; CHECK-LABEL: scalable_of_scalable_2: ; CHECK: // %bb.0: ; CHECK-NEXT: rdvl x8, #1 -; CHECK-NEXT: mov z1.d, #1 // =0x1 -; CHECK-NEXT: mov z2.d, x8 -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: mla z0.d, p0/m, z2.d, z1.d +; CHECK-NEXT: mov z1.d, x8 +; CHECK-NEXT: add z0.d, z0.d, z1.d ; CHECK-NEXT: ret %idx = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer %d = getelementptr <vscale x 2 x i64>, <vscale x 2 x <vscale x 2 x i64>*> %base, <vscale x 2 x i64> %idx _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits