Author: Simon Pilgrim Date: 2020-11-26T15:07:45Z New Revision: 8057ebf4a03f51ed8a7f5c87bbb234ef07ba8f66
URL: https://github.com/llvm/llvm-project/commit/8057ebf4a03f51ed8a7f5c87bbb234ef07ba8f66 DIFF: https://github.com/llvm/llvm-project/commit/8057ebf4a03f51ed8a7f5c87bbb234ef07ba8f66.diff LOG: Revert rG12d59b696b330 "[DAG] Legalize umin(x,y) -> sub(x,usubsat(x,y)) and umax(x,y) -> add(x,usubsat(y,x)) iff usubsat is legal" This reverts commit 12d59b696b33065e070d6ee7a55d2e8c019d138b. Prematurely pushed this to trunk Added: Modified: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/lib/Target/X86/X86ISelLowering.cpp llvm/test/CodeGen/X86/midpoint-int-vec-128.ll Removed: ################################################################################ diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index e45a311f84a4..3464fe87d99f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -7478,26 +7478,10 @@ SDValue TargetLowering::expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const { SDValue Op0 = Node->getOperand(0); SDValue Op1 = Node->getOperand(1); EVT VT = Op0.getValueType(); - unsigned Opcode = Node->getOpcode(); - SDLoc DL(Node); - - // umin(x,y) -> sub(x,usubsat(x,y)) - if (Opcode == ISD::UMIN && isOperationLegal(ISD::SUB, VT) && - isOperationLegal(ISD::USUBSAT, VT)) { - return DAG.getNode(ISD::SUB, DL, VT, Op0, - DAG.getNode(ISD::USUBSAT, DL, VT, Op0, Op1)); - } - - // umax(x,y) -> add(x,usubsat(y,x)) - if (Opcode == ISD::UMAX && isOperationLegal(ISD::ADD, VT) && - isOperationLegal(ISD::USUBSAT, VT)) { - return DAG.getNode(ISD::ADD, DL, VT, Op0, - DAG.getNode(ISD::USUBSAT, DL, VT, Op1, Op0)); - } // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B ISD::CondCode CC; - switch (Opcode) { + switch (Node->getOpcode()) { default: llvm_unreachable("How did we get here?"); case ISD::SMAX: CC = ISD::SETGT; break; case ISD::SMIN: CC = ISD::SETLT; break; @@ -7510,6 +7494,7 @@ SDValue TargetLowering::expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const { if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) return DAG.UnrollVectorOp(Node); + SDLoc DL(Node); SDValue Cond = DAG.getSetCC(DL, VT, Op0, Op1, CC); return DAG.getSelect(DL, VT, Cond, Op0, Op1); } diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5cbca95f45f5..fcbe1330b546 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -26959,6 +26959,22 @@ static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) { if (VT == MVT::v32i16 || VT == MVT::v64i8) return splitVectorIntBinary(Op, DAG); + SDLoc DL(Op); + unsigned Opcode = Op.getOpcode(); + SDValue N0 = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); + + // For pre-SSE41, we can perform UMIN/UMAX v8i16 by using psubusw. + if (VT == MVT::v8i16) { + assert((Opcode == ISD::UMIN || Opcode == ISD::UMAX) && + "Unexpected MIN/MAX opcode"); + if (Opcode == ISD::UMIN) + return DAG.getNode(ISD::SUB, DL, VT, N0, + DAG.getNode(ISD::USUBSAT, DL, VT, N0, N1)); + return DAG.getNode(ISD::ADD, DL, VT, + DAG.getNode(ISD::USUBSAT, DL, VT, N1, N0), N0); + } + // Default to expand. return SDValue(); } diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll index 8ef3f307d0b5..c12d90fee09e 100644 --- a/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll +++ b/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll @@ -2179,8 +2179,8 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun ; SSE2-NEXT: psubusw %xmm1, %xmm2 ; SSE2-NEXT: psubusw %xmm0, %xmm1 ; SSE2-NEXT: psubw %xmm0, %xmm2 -; SSE2-NEXT: paddw %xmm1, %xmm2 ; SSE2-NEXT: paddw %xmm0, %xmm2 +; SSE2-NEXT: paddw %xmm1, %xmm2 ; SSE2-NEXT: psrlw $1, %xmm2 ; SSE2-NEXT: pmullw %xmm3, %xmm2 ; SSE2-NEXT: paddw %xmm0, %xmm2 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits