Author: Simon Pilgrim Date: 2020-12-02T16:29:37Z New Revision: 0dab7ecc5dd1e34267dba4cb1595a70f1d08aa58
URL: https://github.com/llvm/llvm-project/commit/0dab7ecc5dd1e34267dba4cb1595a70f1d08aa58 DIFF: https://github.com/llvm/llvm-project/commit/0dab7ecc5dd1e34267dba4cb1595a70f1d08aa58.diff LOG: [X86] EltsFromConsecutiveLoads - pull out repeated NumLoadedElts. NFCI. Added: Modified: llvm/lib/Target/X86/X86ISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 3020354ca499..eefd7219ae3f 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -8414,7 +8414,8 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts, assert(LDBase && "Did not find base load for merging consecutive loads"); unsigned BaseSizeInBits = EltBaseVT.getStoreSizeInBits(); unsigned BaseSizeInBytes = BaseSizeInBits / 8; - int LoadSizeInBits = (1 + LastLoadedElt - FirstLoadedElt) * BaseSizeInBits; + int NumLoadedElts = (1 + LastLoadedElt - FirstLoadedElt); + int LoadSizeInBits = NumLoadedElts * BaseSizeInBits; assert((BaseSizeInBits % 8) == 0 && "Sub-byte element loads detected"); // TODO: Support offsetting the base load. @@ -8476,7 +8477,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts, // base pointer. If the vector contains zeros, then attempt to shuffle those // elements. if (FirstLoadedElt == 0 && - (LastLoadedElt == (int)(NumElems - 1) || IsDereferenceable) && + (NumLoadedElts == (int)NumElems || IsDereferenceable) && (IsConsecutiveLoad || IsConsecutiveLoadWithZeros)) { if (isAfterLegalize && !TLI.isOperationLegal(ISD::LOAD, VT)) return SDValue(); _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits