Author: Craig Topper Date: 2020-12-02T21:13:42-08:00 New Revision: 1ccd36161d54c098ecb8a6b35695844a16943043
URL: https://github.com/llvm/llvm-project/commit/1ccd36161d54c098ecb8a6b35695844a16943043 DIFF: https://github.com/llvm/llvm-project/commit/1ccd36161d54c098ecb8a6b35695844a16943043.diff LOG: [RISCV] Add additional half precision fnmadd/fnmsub tests with an fneg on the second operand instead of the first. This matches the float/double tests added in defe11866a326491ee9767f84bb3f70cfc4f4bcb Added: Modified: llvm/test/CodeGen/RISCV/half-arith.ll Removed: ################################################################################ diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll index cc94f3e23cc7..ad4978e117cf 100644 --- a/llvm/test/CodeGen/RISCV/half-arith.ll +++ b/llvm/test/CodeGen/RISCV/half-arith.ll @@ -302,6 +302,30 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind { ret half %1 } +define half @fnmadd_s_2(half %a, half %b, half %c) nounwind { +; RV32IZFH-LABEL: fnmadd_s_2: +; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: fmv.h.x ft0, zero +; RV32IZFH-NEXT: fadd.h ft1, fa1, ft0 +; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0 +; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0 +; RV32IZFH-NEXT: ret +; +; RV64IZFH-LABEL: fnmadd_s_2: +; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: fmv.h.x ft0, zero +; RV64IZFH-NEXT: fadd.h ft1, fa1, ft0 +; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0 +; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0 +; RV64IZFH-NEXT: ret + %b_ = fadd half 0.0, %b + %c_ = fadd half 0.0, %c + %negb = fsub half -0.0, %b_ + %negc = fsub half -0.0, %c_ + %1 = call half @llvm.fma.f16(half %a, half %negb, half %negc) + ret half %1 +} + define half @fnmsub_s(half %a, half %b, half %c) nounwind { ; RV32IZFH-LABEL: fnmsub_s: ; RV32IZFH: # %bb.0: @@ -322,6 +346,26 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind { ret half %1 } +define half @fnmsub_s_2(half %a, half %b, half %c) nounwind { +; RV32IZFH-LABEL: fnmsub_s_2: +; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: fmv.h.x ft0, zero +; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0 +; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2 +; RV32IZFH-NEXT: ret +; +; RV64IZFH-LABEL: fnmsub_s_2: +; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: fmv.h.x ft0, zero +; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0 +; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2 +; RV64IZFH-NEXT: ret + %b_ = fadd half 0.0, %b + %negb = fsub half -0.0, %b_ + %1 = call half @llvm.fma.f16(half %a, half %negb, half %c) + ret half %1 +} + define half @fmadd_s_contract(half %a, half %b, half %c) nounwind { ; RV32IZFH-LABEL: fmadd_s_contract: ; RV32IZFH: # %bb.0: _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits