Author: Tomas Matheson Date: 2020-12-18T13:30:46Z New Revision: fc712eb7aa00aabcdafda54776038efdc486d570
URL: https://github.com/llvm/llvm-project/commit/fc712eb7aa00aabcdafda54776038efdc486d570 DIFF: https://github.com/llvm/llvm-project/commit/fc712eb7aa00aabcdafda54776038efdc486d570.diff LOG: [AArch64] Fix Copy Elemination for negative values Redundant Copy Elimination was eliminating a MOVi32imm -1 when it determined that the value of the destination register is already -1. However, it didn't take into account that the MOVi32imm zeroes the upper 32 bits (which are FFFFFFFF) and therefore cannot be eliminated. Reviewed By: paulwalker-arm Differential Revision: https://reviews.llvm.org/D93100 Added: Modified: llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp llvm/test/CodeGen/AArch64/machine-copy-remove.mir Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp index 0d75ab7ac8a9..019220e3a527 100644 --- a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp +++ b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp @@ -408,6 +408,11 @@ bool AArch64RedundantCopyElimination::optimizeBlock(MachineBasicBlock *MBB) { O.getReg() != CmpReg; })) continue; + + // Don't remove a move immediate that implicitly defines the upper + // bits as diff erent. + if (TRI->isSuperRegister(DefReg, KnownReg.Reg) && KnownReg.Imm < 0) + continue; } if (IsCopy) diff --git a/llvm/test/CodeGen/AArch64/machine-copy-remove.mir b/llvm/test/CodeGen/AArch64/machine-copy-remove.mir index 4e3cb3c12806..b2fc40a4d255 100644 --- a/llvm/test/CodeGen/AArch64/machine-copy-remove.mir +++ b/llvm/test/CodeGen/AArch64/machine-copy-remove.mir @@ -536,13 +536,13 @@ body: | bb.2: RET_ReallyLR ... -# Eliminate redundant MOVi32imm -1 in bb.1 +# Don't eliminate redundant MOVi32imm -1 in bb.1: the upper bits are nonzero. # Note: 64-bit compare/32-bit move imm # Kill marker should be removed from compare. # CHECK-LABEL: name: test21 -# CHECK: ADDSXri $x0, 1, 0, implicit-def $nzcv +# CHECK: ADDSXri killed $x0, 1, 0, implicit-def $nzcv # CHECK: bb.1: -# CHECK-NOT: MOVi32imm +# CHECK: MOVi32imm name: test21 tracksRegLiveness: true body: | _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits