Author: Kazushi (Jam) Marukawa Date: 2020-12-19T09:16:43+09:00 New Revision: af83b74dc2e563c429dfcf5bd0a21dd2d4b8af7b
URL: https://github.com/llvm/llvm-project/commit/af83b74dc2e563c429dfcf5bd0a21dd2d4b8af7b DIFF: https://github.com/llvm/llvm-project/commit/af83b74dc2e563c429dfcf5bd0a21dd2d4b8af7b.diff LOG: [VE] Support copy of vector mask registers Support VM and VMP registers in copyPhysReg() function. Also add regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D93547 Added: Modified: llvm/lib/Target/VE/VEInstrInfo.cpp llvm/test/CodeGen/VE/Vector/fastcc_callee.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp index 530c5d655931..9770052ff913 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.cpp +++ b/llvm/lib/Target/VE/VEInstrInfo.cpp @@ -341,6 +341,11 @@ static void copyPhysSubRegs(MachineBasicBlock &MBB, MachineInstrBuilder MIB = BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0); MovMI = MIB.getInstr(); + } else if (MCID.getOpcode() == VE::ANDMmm) { + // generate "ANDM, dest, vm0, src" instruction. + MachineInstrBuilder MIB = + BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc); + MovMI = MIB.getInstr(); } else { llvm_unreachable("Unexpected reg-to-reg copy instruction"); } @@ -379,6 +384,16 @@ void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, .addReg(SrcReg, getKillRegState(KillSrc)) .addReg(SubTmp, getKillRegState(true)); MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true); + } else if (VE::VMRegClass.contains(DestReg, SrcReg)) { + BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) + .addReg(VE::VM0) + .addReg(SrcReg, getKillRegState(KillSrc)); + } else if (VE::VM512RegClass.contains(DestReg, SrcReg)) { + // Use two instructions. + const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd}; + unsigned int NumSubRegs = 2; + copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ANDMmm), + NumSubRegs, SubRegIdx, &getRegisterInfo()); } else if (VE::F128RegClass.contains(DestReg, SrcReg)) { // Use two instructions. const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; diff --git a/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll b/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll index fe601b082192..c0ad247d0e74 100644 --- a/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll +++ b/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll @@ -120,3 +120,20 @@ define fastcc <256 x i32> @vreg_arg_v256i32_r6(<256 x i32> %p0, <256 x i32> %p1, ; define <256 x i32> @vreg_arg_v256i32_r8(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4, <256 x i32> %p5, <256 x i32> %p6, <256 x i32> %p7, <256 x i32> %p8) { ; ret <256 x i32> %p8 ; } + +define fastcc <256 x i1> @vreg_arg_v256i1_vm7(<256 x i1> %vm1, <256 x i1> %vm2, <256 x i1> %vm3, <256 x i1> %vm4, <256 x i1> %vm5, <256 x i1> %vm6, <256 x i1> %vm7, <256 x i1> %vm8) { +; CHECK-LABEL: vreg_arg_v256i1_vm7: +; CHECK: # %bb.0: +; CHECK-NEXT: andm %vm1, %vm0, %vm6 +; CHECK-NEXT: b.l.t (, %s10) + ret <256 x i1> %vm6 +} + +define fastcc <512 x i1> @vreg_arg_v512i1_vmp3(<512 x i1> %vmp1, <512 x i1> %vmp2, <512 x i1> %vmp3, <512 x i1> %vmp4) { +; CHECK-LABEL: vreg_arg_v512i1_vmp3: +; CHECK: # %bb.0: +; CHECK-NEXT: andm %vm2, %vm0, %vm6 +; CHECK-NEXT: andm %vm3, %vm0, %vm7 +; CHECK-NEXT: b.l.t (, %s10) + ret <512 x i1> %vmp3 +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits