Author: Esme-Yi Date: 2020-12-21T06:16:50Z New Revision: 26d378b801fa035d9fd0ff510b031f7c06138c89
URL: https://github.com/llvm/llvm-project/commit/26d378b801fa035d9fd0ff510b031f7c06138c89 DIFF: https://github.com/llvm/llvm-project/commit/26d378b801fa035d9fd0ff510b031f7c06138c89.diff LOG: [PowerPC][NFC] Added assertion of shift exponent is too large for 'uint64_t'. Added: Modified: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index cd609af0ffe6..4ecadfbb1b8a 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -816,8 +816,6 @@ static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl, unsigned LZ = countLeadingZeros<uint64_t>(Imm); unsigned TO = countTrailingOnes<uint64_t>(Imm); unsigned LO = countLeadingOnes<uint64_t>(Imm); - // Count of ones follwing the leading zeros. - unsigned FO = countLeadingOnes<uint64_t>(Imm << LZ); unsigned Hi32 = Hi_32(Imm); unsigned Lo32 = Lo_32(Imm); SDNode *Result = nullptr; @@ -843,6 +841,9 @@ static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl, // Following patterns use 2 instructions to materialize the Imm. InstCnt = 2; + assert(LZ < 64 && "Unexpected leading zeros here."); + // Count of ones follwing the leading zeros. + unsigned FO = countLeadingOnes<uint64_t>(Imm << LZ); // 2-1) Patterns : {zeros}{31-bit value} // {ones}{31-bit value} if (isInt<32>(Imm)) { _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits