Author: Jonas Paulsson Date: 2021-01-11T11:38:23-06:00 New Revision: 171771e0780fd5d028a24f8650a11299478df266
URL: https://github.com/llvm/llvm-project/commit/171771e0780fd5d028a24f8650a11299478df266 DIFF: https://github.com/llvm/llvm-project/commit/171771e0780fd5d028a24f8650a11299478df266.diff LOG: [SystemZ] Minor NFC fix in SchedModels. The unused LRMux opcode was removed by 8f8c381, but a regexp still matched for it in the scheduler files which is now removed. Review: Ulrich Weigand Added: Modified: llvm/lib/Target/SystemZ/SystemZScheduleZ13.td llvm/lib/Target/SystemZ/SystemZScheduleZ14.td llvm/lib/Target/SystemZ/SystemZScheduleZ15.td llvm/lib/Target/SystemZ/SystemZScheduleZ196.td llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td Removed: ################################################################################ diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index b3266051da4e1..de49106a5a601 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -204,7 +204,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLIL(F|H|L)$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(F|H)I$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>; -def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>; +def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR$")>; // Load and zero rightmost byte def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td index df7282a2961b8..5ea269cb891d6 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td @@ -205,7 +205,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLIL(F|H|L)$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(F|H)I$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>; -def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>; +def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR$")>; // Load and zero rightmost byte def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td index 56ceb88f35d4f..6a28aec6f846e 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td @@ -206,7 +206,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLIL(F|H|L)$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(F|H)I$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>; -def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>; +def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR$")>; // Load and zero rightmost byte def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td index ca714ef1a702b..9a306591a34f7 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td @@ -182,7 +182,7 @@ def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLIL(F|H|L)$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "LG(F|H)I$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>; -def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR(Mux)?$")>; +def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR$")>; // Load and test def : InstRW<[WLat1LSU, WLat1LSU, LSU, FXU, NormalGr], (instregex "LT(G)?$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td index fb226be678dad..f3ff1dfaba75c 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -187,7 +187,7 @@ def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLIL(F|H|L)$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "LG(F|H)I$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>; -def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR(Mux)?$")>; +def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR$")>; // Load and trap def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "L(FH|G)?AT$")>; _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits