Author: Bjorn Pettersson Date: 2021-01-11T21:53:56+01:00 New Revision: 32c073acb320db3b22ca76b1e21dd688a70b50e8
URL: https://github.com/llvm/llvm-project/commit/32c073acb320db3b22ca76b1e21dd688a70b50e8 DIFF: https://github.com/llvm/llvm-project/commit/32c073acb320db3b22ca76b1e21dd688a70b50e8.diff LOG: [GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT Before this patch there was generic mapping from vector_extract to G_EXTRACT_VECTOR_ELT added in SelectionDAGCompat.td. That mapping is now replaced by a mapping from extractelt instead. The reasoning is that vector_extract is marked as deprecated, so it is assumed that a majority of targets will use extractelt and not vector_extract (and that the long term solution for all targets would be to use extractelt). Targets like AArch64 that still use vector_extract can add an additional mapping from the deprecated vector_extract as target specific tablegen definitions. Such a mapping is added for AArch64 in this patch to avoid breaking tests. When adding the extractelt => G_EXTRACT_VECTOR_ELT mapping we triggered some new code paths in GlobalISelEmitter, ending up in an assert when trying to import a pattern containing EXTRACT_SUBREG for ARM. Therefore this patch also adds a "failedImport" warning for that situation (instead of hitting the assert). Differential Revision: https://reviews.llvm.org/D93416 Added: Modified: llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td llvm/lib/Target/AArch64/AArch64InstrGISel.td llvm/utils/TableGen/GlobalISelEmitter.cpp Removed: ################################################################################ diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index ff4cf3a5d98d..6fb8a6b15dd7 100644 --- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -116,7 +116,7 @@ def : GINodeEquiv<G_CTTZ, cttz>; def : GINodeEquiv<G_CTLZ_ZERO_UNDEF, ctlz_zero_undef>; def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>; def : GINodeEquiv<G_CTPOP, ctpop>; -def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>; +def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, extractelt>; def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>; def : GINodeEquiv<G_BUILD_VECTOR, build_vector>; def : GINodeEquiv<G_FCEIL, fceil>; diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td index 430155c52302..eadb6847ceb6 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td +++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td @@ -164,6 +164,8 @@ def : GINodeEquiv<G_EXT, AArch64ext>; def : GINodeEquiv<G_VASHR, AArch64vashr>; def : GINodeEquiv<G_VLSHR, AArch64vlshr>; +def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>; + // These are patterns that we only use for GlobalISel via the importer. def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)), (vector_extract (v2f32 FPR64:$Rn), (i64 1)))), diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp index 28c7d8b9634a..c10f85abccc4 100644 --- a/llvm/utils/TableGen/GlobalISelEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp @@ -4690,6 +4690,8 @@ Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderers( // EXTRACT_SUBREG needs to use a subregister COPY. if (Name == "EXTRACT_SUBREG") { + if (!Dst->getChild(1)->isLeaf()) + return failedImport("EXTRACT_SUBREG child #1 is not a leaf"); DefInit *SubRegInit = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue()); if (!SubRegInit) return failedImport("EXTRACT_SUBREG child #1 is not a subreg index"); _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits