Author: Craig Topper Date: 2021-01-12T11:08:26-08:00 New Revision: a14040bd4d902419b53cf0ad576caa0f01eccf5c
URL: https://github.com/llvm/llvm-project/commit/a14040bd4d902419b53cf0ad576caa0f01eccf5c DIFF: https://github.com/llvm/llvm-project/commit/a14040bd4d902419b53cf0ad576caa0f01eccf5c.diff LOG: [RISCV] Use vmerge.vim for llvm.riscv.vfmerge with a 0.0 scalar operand. We can use a 0 immediate to avoid needing to materialize 0 into an FPR first. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D94459 Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index bf5ee06bce35..3604a25b0d6a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -3367,6 +3367,14 @@ defm "" : VPatBinaryV_VM<"int_riscv_vfmerge", "PseudoVMERGE", defm "" : VPatBinaryV_XM<"int_riscv_vfmerge", "PseudoVFMERGE", /*CarryOut = */0, /*vtilist=*/AllFloatVectors>; +foreach fvti = AllFloatVectors in { + defvar instr = !cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX); + def : Pat<(fvti.Vector (int_riscv_vfmerge (fvti.Vector fvti.RegClass:$rs2), + (fvti.Scalar (fpimm0)), + (fvti.Mask V0), (XLenVT GPR:$vl))), + (instr fvti.RegClass:$rs2, 0, (fvti.Mask V0), (NoX0 GPR:$vl), fvti.SEW)>; +} + //===----------------------------------------------------------------------===// // 14.16. Vector Floating-Point Move Instruction //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll index a6b09704c8a6..5a7262c348c5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll @@ -439,3 +439,157 @@ entry: ret <vscale x 16 x float> %a } + +define <vscale x 1 x half> @intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16( + <vscale x 1 x half> %0, + half zeroinitializer, + <vscale x 1 x i1> %1, + i32 %2) + + ret <vscale x 1 x half> %a +} + +define <vscale x 2 x half> @intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16( + <vscale x 2 x half> %0, + half zeroinitializer, + <vscale x 2 x i1> %1, + i32 %2) + + ret <vscale x 2 x half> %a +} + +define <vscale x 4 x half> @intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16( + <vscale x 4 x half> %0, + half zeroinitializer, + <vscale x 4 x i1> %1, + i32 %2) + + ret <vscale x 4 x half> %a +} + +define <vscale x 8 x half> @intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16( + <vscale x 8 x half> %0, + half zeroinitializer, + <vscale x 8 x i1> %1, + i32 %2) + + ret <vscale x 8 x half> %a +} + +define <vscale x 16 x half> @intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16( + <vscale x 16 x half> %0, + half zeroinitializer, + <vscale x 16 x i1> %1, + i32 %2) + + ret <vscale x 16 x half> %a +} + +define <vscale x 32 x half> @intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x i1> %1, i32 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16( + <vscale x 32 x half> %0, + half zeroinitializer, + <vscale x 32 x i1> %1, + i32 %2) + + ret <vscale x 32 x half> %a +} + +define <vscale x 1 x float> @intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x i1> %1, i32 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32( + <vscale x 1 x float> %0, + float zeroinitializer, + <vscale x 1 x i1> %1, + i32 %2) + + ret <vscale x 1 x float> %a +} + +define <vscale x 2 x float> @intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x i1> %1, i32 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32( + <vscale x 2 x float> %0, + float zeroinitializer, + <vscale x 2 x i1> %1, + i32 %2) + + ret <vscale x 2 x float> %a +} + +define <vscale x 4 x float> @intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %1, i32 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32( + <vscale x 4 x float> %0, + float zeroinitializer, + <vscale x 4 x i1> %1, + i32 %2) + + ret <vscale x 4 x float> %a +} + +define <vscale x 8 x float> @intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x i1> %1, i32 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32( + <vscale x 8 x float> %0, + float zeroinitializer, + <vscale x 8 x i1> %1, + i32 %2) + + ret <vscale x 8 x float> %a +} + +define <vscale x 16 x float> @intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x i1> %1, i32 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32( + <vscale x 16 x float> %0, + float zeroinitializer, + <vscale x 16 x i1> %1, + i32 %2) + + ret <vscale x 16 x float> %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll index 6f3cafce40e6..1a344e1cc0fa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll @@ -599,3 +599,213 @@ entry: ret <vscale x 8 x double> %a } + +define <vscale x 1 x half> @intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16( + <vscale x 1 x half> %0, + half zeroinitializer, + <vscale x 1 x i1> %1, + i64 %2) + + ret <vscale x 1 x half> %a +} + +define <vscale x 2 x half> @intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16( + <vscale x 2 x half> %0, + half zeroinitializer, + <vscale x 2 x i1> %1, + i64 %2) + + ret <vscale x 2 x half> %a +} + +define <vscale x 4 x half> @intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16( + <vscale x 4 x half> %0, + half zeroinitializer, + <vscale x 4 x i1> %1, + i64 %2) + + ret <vscale x 4 x half> %a +} + +define <vscale x 8 x half> @intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16( + <vscale x 8 x half> %0, + half zeroinitializer, + <vscale x 8 x i1> %1, + i64 %2) + + ret <vscale x 8 x half> %a +} + +define <vscale x 16 x half> @intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16( + <vscale x 16 x half> %0, + half zeroinitializer, + <vscale x 16 x i1> %1, + i64 %2) + + ret <vscale x 16 x half> %a +} + +define <vscale x 32 x half> @intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16( + <vscale x 32 x half> %0, + half zeroinitializer, + <vscale x 32 x i1> %1, + i64 %2) + + ret <vscale x 32 x half> %a +} + +define <vscale x 1 x float> @intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32( + <vscale x 1 x float> %0, + float zeroinitializer, + <vscale x 1 x i1> %1, + i64 %2) + + ret <vscale x 1 x float> %a +} + +define <vscale x 2 x float> @intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32( + <vscale x 2 x float> %0, + float zeroinitializer, + <vscale x 2 x i1> %1, + i64 %2) + + ret <vscale x 2 x float> %a +} + +define <vscale x 4 x float> @intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32( + <vscale x 4 x float> %0, + float zeroinitializer, + <vscale x 4 x i1> %1, + i64 %2) + + ret <vscale x 4 x float> %a +} + +define <vscale x 8 x float> @intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32( + <vscale x 8 x float> %0, + float zeroinitializer, + <vscale x 8 x i1> %1, + i64 %2) + + ret <vscale x 8 x float> %a +} + +define <vscale x 16 x float> @intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32( + <vscale x 16 x float> %0, + float zeroinitializer, + <vscale x 16 x i1> %1, + i64 %2) + + ret <vscale x 16 x float> %a +} + +define <vscale x 1 x double> @intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.f64( + <vscale x 1 x double> %0, + double zeroinitializer, + <vscale x 1 x i1> %1, + i64 %2) + + ret <vscale x 1 x double> %a +} + +define <vscale x 2 x double> @intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.f64( + <vscale x 2 x double> %0, + double zeroinitializer, + <vscale x 2 x i1> %1, + i64 %2) + + ret <vscale x 2 x double> %a +} + +define <vscale x 4 x double> @intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.f64( + <vscale x 4 x double> %0, + double zeroinitializer, + <vscale x 4 x i1> %1, + i64 %2) + + ret <vscale x 4 x double> %a +} + +define <vscale x 8 x double> @intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x i1> %1, i64 %2) nounwind { +entry: +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64 +; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu +; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 + %a = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64( + <vscale x 8 x double> %0, + double zeroinitializer, + <vscale x 8 x i1> %1, + i64 %2) + + ret <vscale x 8 x double> %a +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits