Author: Amara Emerson Date: 2021-01-15T01:10:49-08:00 New Revision: 89e84dec1879417fb7eb96edaa55dac7eca204ab
URL: https://github.com/llvm/llvm-project/commit/89e84dec1879417fb7eb96edaa55dac7eca204ab DIFF: https://github.com/llvm/llvm-project/commit/89e84dec1879417fb7eb96edaa55dac7eca204ab.diff LOG: [AArch64][GlobalISel] Fix fallbacks introduced for G_SITOFP in 8f283cafddfa8d6d01a94b48cdc5d25817569e91 If we have an integer->fp convert that has differing sizes, e.g. s32 to s64, then don't try to convert it to AArch64::G_SITOF since it won't select. Added: Modified: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index 5dcb9b2d00da..797f33ce2ab4 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -1947,8 +1947,11 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) { // Otherwise, it ends up matching an fpr/gpr variant and adding a cross-bank // copy. Register SrcReg = I.getOperand(1).getReg(); - if (MRI.getType(SrcReg).isVector()) + LLT SrcTy = MRI.getType(SrcReg); + LLT DstTy = MRI.getType(I.getOperand(0).getReg()); + if (SrcTy.isVector() || SrcTy.getSizeInBits() != DstTy.getSizeInBits()) return false; + if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::FPRRegBankID) { if (I.getOpcode() == TargetOpcode::G_SITOFP) I.setDesc(TII.get(AArch64::G_SITOF)); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir index aad71bd99f8f..4274f91dba49 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir @@ -327,6 +327,29 @@ body: | $d0 = COPY %1(s64) ... +--- +name: sitofp_s64_s32_fpr_both +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + +body: | + bb.0: + liveins: $s0 + + ; CHECK-LABEL: name: sitofp_s64_s32_fpr + ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY]] + ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY2]] + ; CHECK: $d0 = COPY [[SCVTFUWDri]] + %0(s32) = COPY $s0 + %1(s64) = G_SITOFP %0 + $d0 = COPY %1(s64) +... + --- name: sitofp_s64_s64_fpr legalized: true _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits