Author: Craig Topper Date: 2021-01-23T15:57:41-08:00 New Revision: 998057ec06ae7e0fb1e0be0f2702df4d6338a128
URL: https://github.com/llvm/llvm-project/commit/998057ec06ae7e0fb1e0be0f2702df4d6338a128 DIFF: https://github.com/llvm/llvm-project/commit/998057ec06ae7e0fb1e0be0f2702df4d6338a128.diff LOG: [RISCV] Add isel patterns to remove masks on SLO/SRO shift amounts. Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoB.td llvm/test/CodeGen/RISCV/rv32Zbp.ll llvm/test/CodeGen/RISCV/rv64Zbp.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td index f075699c17f0..8740e61b1ee1 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -694,9 +694,9 @@ def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtZbbOrZbp] let Predicates = [HasStdExtZbp] in { -def : Pat<(not (shl (not GPR:$rs1), GPR:$rs2)), +def : Pat<(not (shiftop<shl> (not GPR:$rs1), GPR:$rs2)), (SLO GPR:$rs1, GPR:$rs2)>; -def : Pat<(not (srl (not GPR:$rs1), GPR:$rs2)), +def : Pat<(not (shiftop<srl> (not GPR:$rs1), GPR:$rs2)), (SRO GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtZbp] @@ -960,9 +960,9 @@ def : Pat<(add (SLLIUWPat GPR:$rs1, (XLenVT 3)), GPR:$rs2), } // Predicates = [HasStdExtZba, IsRV64] let Predicates = [HasStdExtZbp, IsRV64] in { -def : Pat<(not (riscv_sllw (not GPR:$rs1), GPR:$rs2)), +def : Pat<(not (shiftopw<riscv_sllw> (not GPR:$rs1), GPR:$rs2)), (SLOW GPR:$rs1, GPR:$rs2)>; -def : Pat<(not (riscv_srlw (not GPR:$rs1), GPR:$rs2)), +def : Pat<(not (shiftopw<riscv_srlw> (not GPR:$rs1), GPR:$rs2)), (SROW GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtZbp, IsRV64] diff --git a/llvm/test/CodeGen/RISCV/rv32Zbp.ll b/llvm/test/CodeGen/RISCV/rv32Zbp.ll index 8fc772931f3a..de315dfb2d5a 100644 --- a/llvm/test/CodeGen/RISCV/rv32Zbp.ll +++ b/llvm/test/CodeGen/RISCV/rv32Zbp.ll @@ -39,13 +39,11 @@ define i32 @slo_i32_mask(i32 %a, i32 %b) nounwind { ; ; RV32IB-LABEL: slo_i32_mask: ; RV32IB: # %bb.0: -; RV32IB-NEXT: andi a1, a1, 31 ; RV32IB-NEXT: slo a0, a0, a1 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: slo_i32_mask: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: andi a1, a1, 31 ; RV32IBP-NEXT: slo a0, a0, a1 ; RV32IBP-NEXT: ret %neg = xor i32 %a, -1 @@ -243,13 +241,11 @@ define i32 @sro_i32_mask(i32 %a, i32 %b) nounwind { ; ; RV32IB-LABEL: sro_i32_mask: ; RV32IB: # %bb.0: -; RV32IB-NEXT: andi a1, a1, 31 ; RV32IB-NEXT: sro a0, a0, a1 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: sro_i32_mask: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: andi a1, a1, 31 ; RV32IBP-NEXT: sro a0, a0, a1 ; RV32IBP-NEXT: ret %neg = xor i32 %a, -1 diff --git a/llvm/test/CodeGen/RISCV/rv64Zbp.ll b/llvm/test/CodeGen/RISCV/rv64Zbp.ll index 243ebc17a86b..d2191afd5b79 100644 --- a/llvm/test/CodeGen/RISCV/rv64Zbp.ll +++ b/llvm/test/CodeGen/RISCV/rv64Zbp.ll @@ -86,13 +86,11 @@ define i64 @slo_i64_mask(i64 %a, i64 %b) nounwind { ; ; RV64IB-LABEL: slo_i64_mask: ; RV64IB: # %bb.0: -; RV64IB-NEXT: andi a1, a1, 63 ; RV64IB-NEXT: slo a0, a0, a1 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: slo_i64_mask: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: andi a1, a1, 63 ; RV64IBP-NEXT: slo a0, a0, a1 ; RV64IBP-NEXT: ret %neg = xor i64 %a, -1 @@ -182,13 +180,11 @@ define i64 @sro_i64_mask(i64 %a, i64 %b) nounwind { ; ; RV64IB-LABEL: sro_i64_mask: ; RV64IB: # %bb.0: -; RV64IB-NEXT: andi a1, a1, 63 ; RV64IB-NEXT: sro a0, a0, a1 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: sro_i64_mask: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: andi a1, a1, 63 ; RV64IBP-NEXT: sro a0, a0, a1 ; RV64IBP-NEXT: ret %neg = xor i64 %a, -1 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits