Author: Craig Topper Date: 2021-01-24T10:41:58-08:00 New Revision: 116177afcce88d807c1beffcb9221999ad8a69a9
URL: https://github.com/llvm/llvm-project/commit/116177afcce88d807c1beffcb9221999ad8a69a9 DIFF: https://github.com/llvm/llvm-project/commit/116177afcce88d807c1beffcb9221999ad8a69a9.diff LOG: [RISCV] Use SRLIWPat in the PACKUW pattern. This makes the code more tolerant if we ever change SimplifyDemandedBits to not remove 1s from the lsbs of a contiguous mask. Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoB.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td index 9940063d5f9a..501137a934d6 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -1046,7 +1046,6 @@ def : Pat<(sext_inreg (or (shl GPR:$rs2, (i64 16)), i32), (PACKW GPR:$rs1, GPR:$rs2)>; def : Pat<(or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000), - (srl (and GPR:$rs1, 0x00000000FFFF0000), - (i64 16))), + (SRLIWPat GPR:$rs1, (i64 16))), (PACKUW GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtZbp, IsRV64] _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits