Author: Albion Date: 2021-06-25T15:39:21-04:00 New Revision: 26cbf3df08742d8c5c7c69022d2a741bfe443fee
URL: https://github.com/llvm/llvm-project/commit/26cbf3df08742d8c5c7c69022d2a741bfe443fee DIFF: https://github.com/llvm/llvm-project/commit/26cbf3df08742d8c5c7c69022d2a741bfe443fee.diff LOG: Added 64bit test Added: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll Modified: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll Removed: ################################################################################ diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll new file mode 100644 index 000000000000..c70a99fca936 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll @@ -0,0 +1,76 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=pwr9 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: -mcpu=pwr9 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \ +; RUN: -mcpu=pwr9 < %s | FileCheck %s + +; tdw +declare void @llvm.ppc.tdw(i64 %a, i64 %b, i32 immarg) +define dso_local void @test__tdwlgt(i64 %a, i64 %b) { + call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 1) + ret void +} + +define dso_local void @test__tdwllt(i64 %a, i64 %b) { + call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 2) + ret void +} + +define dso_local void @test__tdweq(i64 %a, i64 %b) { + call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 4) + ret void +} + +define dso_local void @test__tdwlge(i64 %a, i64 %b) { + call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 5) + ret void +} + +define dso_local void @test__tdwlle(i64 %a, i64 %b) { + call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 6) + ret void +} + +define dso_local void @test__tdwgt(i64 %a, i64 %b) { + call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 8) + ret void +} + +define dso_local void @test__tdwge(i64 %a, i64 %b) { + call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 12) + ret void +} + +define dso_local void @test__tdwlt(i64 %a, i64 %b) { + call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 16) + ret void +} + +define dso_local void @test__tdwle(i64 %a, i64 %b) { + call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 20) + ret void +} + +define dso_local void @test__tdwne24(i64 %a, i64 %b) { + call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 24) + ret void +} + +define dso_local void @test__tdweq31(i64 %a, i64 %b) { + call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 31) + ret void +} + +define dso_local void @test__tdw_no_match(i64 %a, i64 %b) { + call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 13) + ret void +} + +; trapd +declare void @llvm.ppc.trapd(i64 %a) +define dso_local void @test__trapd(i64 %a) { + call void @llvm.ppc.trapd(i64 %a) + ret void +} \ No newline at end of file diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll index 1407dbf1db5f..9ed579381784 100644 --- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll +++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll @@ -1,76 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64 +; RUN: -mcpu=pwr9 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64 +; RUN: -mcpu=pwr9 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \ -; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32 +; RUN: -mcpu=pwr9 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \ -; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64 - -; tdw -#ifndef __PPC64__ -declare void @llvm.ppc.tdw(i64 %a, i64 %b, i32 immarg) -define dso_local void @test__tdwlgt(i64 %a, i64 %b) { - call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 1) - ret void -} - -define dso_local void @test__tdwllt(i64 %a, i64 %b) { - call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 2) - ret void -} - -define dso_local void @test__tdweq(i64 %a, i64 %b) { - call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 4) - ret void -} - -define dso_local void @test__tdwlge(i64 %a, i64 %b) { - call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 5) - ret void -} - -define dso_local void @test__tdwlle(i64 %a, i64 %b) { - call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 6) - ret void -} - -define dso_local void @test__tdwgt(i64 %a, i64 %b) { - call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 8) - ret void -} - -define dso_local void @test__tdwge(i64 %a, i64 %b) { - call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 12) - ret void -} - -define dso_local void @test__tdwlt(i64 %a, i64 %b) { - call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 16) - ret void -} - -define dso_local void @test__tdwle(i64 %a, i64 %b) { - call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 20) - ret void -} - -define dso_local void @test__tdwne24(i64 %a, i64 %b) { - call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 24) - ret void -} - -define dso_local void @test__tdweq31(i64 %a, i64 %b) { - call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 31) - ret void -} - -define dso_local void @test__tdw_no_match(i64 %a, i64 %b) { - call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 13) - ret void -} -#endif +; RUN: -mcpu=pwr9 < %s | FileCheck %s ; tw declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c) @@ -145,10 +81,3 @@ define dso_local void @test__trap(i32 %a) { call void @llvm.ppc.trap(i32 %a) ret void } - -; trapd -declare void @llvm.ppc.trapd(i64 %a) -define dso_local void @test__trapd(i64 %a) { - call void @llvm.ppc.trapd(i64 %a) - ret void -} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
