Author: Jonas Hahnfeld Date: 2022-08-23T19:09:38+02:00 New Revision: 69c35fa29af3d4695cde7654536465b760f19340
URL: https://github.com/llvm/llvm-project/commit/69c35fa29af3d4695cde7654536465b760f19340 DIFF: https://github.com/llvm/llvm-project/commit/69c35fa29af3d4695cde7654536465b760f19340.diff LOG: [RISCV] Re-enable JIT support Commit 8922adf646 recently made JITTargetMachineBuilder honor the hasJIT property of the target. LLVM supports just-in-time compilation on RISC-V, so set the flag. Differential Revision: https://reviews.llvm.org/D131617 (cherry picked from commit 940733d6a0a92245912361bf116514172a15f4f8) Added: Modified: llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp b/llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp index 27d1326d5f6c4..7b63b060dd9c1 100644 --- a/llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp +++ b/llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp @@ -21,8 +21,8 @@ Target &llvm::getTheRISCV64Target() { } extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetInfo() { - RegisterTarget<Triple::riscv32> X(getTheRISCV32Target(), "riscv32", - "32-bit RISC-V", "RISCV"); - RegisterTarget<Triple::riscv64> Y(getTheRISCV64Target(), "riscv64", - "64-bit RISC-V", "RISCV"); + RegisterTarget<Triple::riscv32, /*HasJIT=*/true> X( + getTheRISCV32Target(), "riscv32", "32-bit RISC-V", "RISCV"); + RegisterTarget<Triple::riscv64, /*HasJIT=*/true> Y( + getTheRISCV64Target(), "riscv64", "64-bit RISC-V", "RISCV"); } _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
