Author: Alex Bradbury Date: 2022-09-05T10:48:03+01:00 New Revision: 4ba6a9c9f65bbc8bd06e3652cb20fd4dfc846137
URL: https://github.com/llvm/llvm-project/commit/4ba6a9c9f65bbc8bd06e3652cb20fd4dfc846137 DIFF: https://github.com/llvm/llvm-project/commit/4ba6a9c9f65bbc8bd06e3652cb20fd4dfc846137.diff LOG: [RISCV][ReleaseNotes] Added LLVM and Clang release notes for RISC-V 15.0.0 Added: Modified: clang/docs/ReleaseNotes.rst llvm/docs/ReleaseNotes.rst Removed: ################################################################################ diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 14360b4c4ab64..5620cb3b64004 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -662,6 +662,20 @@ Arm and AArch64 Support in Clang Operations found in the :ref:`Clang Language Extensions <Vector Operations>` document. +RISC-V Support in Clang +----------------------- + +- Updates to the RISC-V vector intrinsics to align with ongoing additions to + the RISC-V Vector intrinsics specification. Additionally, these intrinsics + are now generated lazily, resulting a substantial improvement in + compile-time for code including the vector intrinsics header. +- Intrinsics added for the RISC-V scalar crypto ('K') extensions. +- Intrinsics added for the RISC-V CLZ and CTZ instructions in the Zbb + extension. +- An ABI lowering bug (resulting in incorrect LLVM IR generation) was fixed. + The bug could be triggered in particular circumstances in C++ when passing a + data-only struct that inherits from another struct. + SPIR-V Support in Clang ----------------------- diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 73e065864bdb2..9324d26cbdd81 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -195,7 +195,32 @@ AIX improvements: Changes to the RISC-V Backend ----------------------------- -* The Zvfh extension was added. +* A RISCVRedundantCopyElimination pass was added to remove unnecessary zero + copies. +* A RISC-V specific CodeGenPrepare pass was added. +* The machine outliner was enabled by default for RISC-V at ``-Oz``. + Additionally, the newly introduced RISCVMakeCompressible pass will make + modify instructions prior to emission at ``-Oz`` in order to increase + opportunities for the compression with the RISC-V C extension. +* Various bug fixes and improvements to code generation for the RISC-V vector + extensions. +* Various improvements were made to RISC-V specific optimisation passes such + as RISCVSExtWRemoval and RISCVMergeBaseOffset. +* llc now computes the target ABI based on the target architecture using the + same logic as Clang if not explicit ABI is given. +* ``generic`` is now recognized as a valid CPU name and is mapped to + ``generic-rv32`` or ``generic-rv64`` depending on the target triple. +* Support for the experimental Zvfh extension was added, enabling + half-precision floating point in vectors. +* Support for the Zihintpause (Pause Hint) extension. +* Assembler and disassembler support for the Zfinx and Zdinx (float / double + in integer register) extensions. +* Assembler and disassembler support for the Zicbom, Zicboz, and Zicbop cache + management operation extensions. +* Support for the Zmmul extension (a subextension of the M extension, adding + multiplication instructions only). +* Assembler and disassembler support for the hypervisor extension and for the + Sinval supervisor memory-management extension. Changes to the WebAssembly Backend ---------------------------------- _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits