Author: Nelson Chu Date: 2022-11-14T23:51:16-08:00 New Revision: 868160ad5f7ced95ab55f7037efd4b39fc8ac7e7
URL: https://github.com/llvm/llvm-project/commit/868160ad5f7ced95ab55f7037efd4b39fc8ac7e7 DIFF: https://github.com/llvm/llvm-project/commit/868160ad5f7ced95ab55f7037efd4b39fc8ac7e7.diff LOG: [SiFive] Minimal architecture support for xsfvcp. This patch just let clang/llvm recognizes the xsfvcp extension name with default 0.1 version, but we actually havn't supported it. The imply rule of xsfvcp isn't clear for now, so just ignore it. Added: Modified: llvm/lib/Support/RISCVISAInfo.cpp llvm/lib/Target/RISCV/RISCV.td llvm/lib/Target/RISCV/RISCVSubtarget.h llvm/test/MC/RISCV/attribute-arch.s Removed: ################################################################################ diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 0d93249b09406..8701d70e5f24c 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -105,6 +105,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"svnapot", RISCVExtensionVersion{1, 0}}, {"svinval", RISCVExtensionVersion{1, 0}}, {"xventanacondops", RISCVExtensionVersion{1, 0}}, + {"xsfvcp", RISCVExtensionVersion{0, 1}}, }; static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 3742eb06fc8e6..241e15fecf91b 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -424,6 +424,14 @@ def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()" AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps), "'XVentanaCondOps' (Ventana Conditional Ops)">; +def FeatureStdExtXsfvcp + : SubtargetFeature<"xsfvcp", "HasExtXsfvcp", "true", + "Xsfvcp (Support SiFive custom vector coprocessor interface instructions)", + []>; // FIXME: Need which implication? +def HasExtXsfvcp : Predicate<"Subtarget->hasExtXsfvcp()">, + AssemblerPredicate<(all_of FeatureStdExtXsfvcp), + "'Xsfvcp' (SiFive custom vector coprocessor interface instructions)">; + //===----------------------------------------------------------------------===// // LLVM specific features and extensions //===----------------------------------------------------------------------===// @@ -432,6 +440,7 @@ def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()" // tuning CPU names. def Feature32Bit : SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">; + def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 418c878d10af4..8169e478f4987 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -62,6 +62,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { bool HasStdExtZve64x = false; bool HasStdExtZve64f = false; bool HasStdExtZve64d = false; + bool HasExtXsfvcp = false; bool HasStdExtZvfh = false; bool HasStdExtZfhmin = false; bool HasStdExtZfh = false; @@ -167,6 +168,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { bool hasStdExtZbs() const { return HasStdExtZbs; } bool hasStdExtZca() const { return HasStdExtZca; } bool hasStdExtZvl() const { return ZvlLen != 0; } + bool hasExtXsfvcp() const { return HasExtXsfvcp; } bool hasStdExtZvfh() const { return HasStdExtZvfh; } bool hasStdExtZfhmin() const { return HasStdExtZfhmin; } bool hasStdExtZfh() const { return HasStdExtZfh; } diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index af34567929d60..2d8509ffd3ac8 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -176,6 +176,9 @@ .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0" # CHECK: attribute 5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0" +.attribute arch, "rv64i_xsfvcp" +# CHECK: attribute 5, "rv64i2p0_xsfvcp0p1" + .attribute arch, "rv32izca0p70" # CHECK: attribute 5, "rv32i2p0_zca0p70" _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits