https://github.com/tstellar updated https://github.com/llvm/llvm-project/pull/90805
>From d9a7e5179a89624f23d8d6993e7e9ec8887063fc Mon Sep 17 00:00:00 2001 From: Nikita Popov <npo...@redhat.com> Date: Thu, 2 May 2024 09:38:09 +0900 Subject: [PATCH] [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705) Vectors are always tightly packed, and elements of non-byte-sized usually do not have a well-defined (byte) offset. Fixes https://github.com/llvm/llvm-project/issues/90695. (cherry picked from commit d484c4d3501a7ff3d00a6e0cfad026a3b01d320c) --- .../CodeGen/InterleavedLoadCombinePass.cpp | 3 +++ .../interleaved-load-combine-pr90695.ll | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp index f2d5c3c867c2d..bbb0b654dc67b 100644 --- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp +++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp @@ -877,6 +877,9 @@ struct VectorInfo { if (LI->isAtomic()) return false; + if (!DL.typeSizeEqualsStoreSize(Result.VTy->getElementType())) + return false; + // Get the base polynomial computePolynomialFromPointer(*LI->getPointerOperand(), Offset, BasePtr, DL); diff --git a/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll new file mode 100644 index 0000000000000..ee75b3a083f71 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll @@ -0,0 +1,19 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S -passes=interleaved-load-combine < %s | FileCheck %s + +target triple = "aarch64-unknown-windows-gnu" + +; Make sure we don't crash on loads of vectors of non-byte-sized types. +define <4 x i1> @test(ptr %p) { +; CHECK-LABEL: define <4 x i1> @test( +; CHECK-SAME: ptr [[P:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[LOAD:%.*]] = load <2 x i1>, ptr [[P]], align 1 +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i1> [[LOAD]], <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2> +; CHECK-NEXT: ret <4 x i1> [[SHUF]] +; +entry: + %load = load <2 x i1>, ptr %p, align 1 + %shuf = shufflevector <2 x i1> %load, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2> + ret <4 x i1> %shuf +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
