llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-sparc Author: Koakuma (koachan) <details> <summary>Changes</summary> This adds support for `prefetcha` instruction for prefetching from alternate address spaces. --- Full diff: https://github.com/llvm/llvm-project/pull/94250.diff 3 Files Affected: - (modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+7) - (modified) llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt (+5) - (modified) llvm/test/MC/Sparc/sparcv9-instructions.s (+30) ``````````diff diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index f1778f2162f8c..cac96a1398721 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -1782,6 +1782,13 @@ let Predicates = [HasV9] in { def PREFETCHi : F3_2<3, 0b101101, (outs), (ins (MEMri $rs1, $simm13):$addr, PrefetchTag:$rd), "prefetch [$addr], $rd", []>; + def PREFETCHAr : F3_1_asi<3, 0b111101, (outs), + (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi, PrefetchTag:$rd), + "prefetcha [$addr] $asi, $rd", []>; + let Uses = [ASR3] in + def PREFETCHAi : F3_2<3, 0b111101, (outs), + (ins (MEMri $rs1, $simm13):$addr, PrefetchTag:$rd), + "prefetcha [$addr] %asi, $rd", []>; } diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt b/llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt index 9286814552cf5..1d1fdb667fafa 100644 --- a/llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt +++ b/llvm/test/MC/Disassembler/Sparc/sparc-v9-asi.txt @@ -32,3 +32,8 @@ 0xd5 0xf6 0x11 0x56 # V9: casxa [%i0] #ASI_SNF_L, %l6, %o2 0xd5 0xf6 0x11 0x76 + +# V9: prefetcha [%i1+3968] %asi, #one_read +0xc3 0xee 0x6f 0x80 +# V9: prefetcha [%i1+%i2] #ASI_SNF, #one_read +0xc3 0xee 0x50 0x7a diff --git a/llvm/test/MC/Sparc/sparcv9-instructions.s b/llvm/test/MC/Sparc/sparcv9-instructions.s index f0348eb70f1c5..ae8646f8bc560 100644 --- a/llvm/test/MC/Sparc/sparcv9-instructions.s +++ b/llvm/test/MC/Sparc/sparcv9-instructions.s @@ -557,6 +557,36 @@ ! V9: prefetch [%i1+%i2], #one_read ! encoding: [0xc3,0x6e,0x40,0x1a] prefetch [ %i1 + %i2 ], #one_read + ! V8: error: malformed ASI tag, must be a constant integer expression + ! V8-NEXT: prefetcha [ %i1 + 0xf80 ] %asi, 1 + ! V9: prefetcha [%i1+3968] %asi, #one_read ! encoding: [0xc3,0xee,0x6f,0x80] + prefetcha [ %i1 + 0xf80 ] %asi, 1 + + ! V8: error: malformed ASI tag, must be a constant integer expression + ! V8-NEXT: prefetcha [ %i1 + 0xf80 ] %asi, #one_read + ! V9: prefetcha [%i1+3968] %asi, #one_read ! encoding: [0xc3,0xee,0x6f,0x80] + prefetcha [ %i1 + 0xf80 ] %asi, #one_read + + ! V8: error: malformed ASI tag, must be a constant integer expression + ! V8-NEXT: prefetcha [ %i1 + %i2 ] #ASI_SNF, 1 + ! V9: prefetcha [%i1+%i2] #ASI_SNF, #one_read ! encoding: [0xc3,0xee,0x50,0x7a] + prefetcha [ %i1 + %i2 ] #ASI_SNF, 1 + + ! V8: error: malformed ASI tag, must be a constant integer expression + ! V8-NEXT: prefetcha [ %i1 + %i2 ] #ASI_SNF, #one_read + ! V9: prefetcha [%i1+%i2] #ASI_SNF, #one_read ! encoding: [0xc3,0xee,0x50,0x7a] + prefetcha [ %i1 + %i2 ] #ASI_SNF, #one_read + + ! V8: error: invalid operand for instruction + ! V8-NEXT: prefetcha [ %i1 + %i2 ] 131, 1 + ! V9: prefetcha [%i1+%i2] #ASI_SNF, #one_read ! encoding: [0xc3,0xee,0x50,0x7a] + prefetcha [ %i1 + %i2 ] 131, 1 + + ! V8: error: unexpected token + ! V8-NEXT: prefetcha [ %i1 + %i2 ] 131, #one_read + ! V9: prefetcha [%i1+%i2] #ASI_SNF, #one_read ! encoding: [0xc3,0xee,0x50,0x7a] + prefetcha [ %i1 + %i2 ] 131, #one_read + ! V8: error: instruction requires a CPU feature not currently enabled ! V8-NEXT: done ! V9: done ! encoding: [0x81,0xf0,0x00,0x00] `````````` </details> https://github.com/llvm/llvm-project/pull/94250 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
