================
@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma
vsetvli a2, a0, e32, mf2, ta, ma
# CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible
with all RVV implementations{{$}}
# CHECK-ENCODING: [0x57,0x76,0x75,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for
Application Processors), 'Zve32x' (Vector Extensions for Embedded
Processors){{$}}
# CHECK-UNKNOWN: 0d757657 <unknown>
vsetvli a2, a0, e32, mf4, ta, ma
# CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 8 may not be compatible with
all RVV implementations{{$}}
----------------
lukel97 wrote:
Ok, that seems reasonable. Should we maybe then reword the LMUL < SEWMIN/ELEN
case to mention that the encoding is actually reserved, whereas for SEW > LMUL
* ELEN it may just not be compatible
https://github.com/llvm/llvm-project/pull/94313
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