https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144705
>From b6dc4685321a268bfd70e7c35770c4c57f1bdacf Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Wed, 18 Jun 2025 22:24:53 +0900
Subject: [PATCH 1/2] ARM: Avoid using isTarget wrappers around Triple
predicates
These are module level properties, and querying them through
a function-level subtarget context is confusing. Plus we don't
need an aliased name. This doesn't avoid all the uses, just the
ones in the TargetLowering constructor.
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 28 ++++++++++++-------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 91fb7bc4578b3..f18bdde53cd5d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -515,7 +515,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setBooleanContents(ZeroOrOneBooleanContent);
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
- if (Subtarget->isTargetMachO()) {
+ const Triple &TT = TM.getTargetTriple();
+
+ if (TT.isOSBinFormatMachO()) {
// Uses VFP for Thumb libfuncs if available.
if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
@@ -589,8 +591,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// RTLIB
if (TM.isAAPCS_ABI() &&
- (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
- Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
+ (TT.isTargetAEABI() || TT.isTargetGNUAEABI() || TT.isTargetMuslAEABI() ||
+ TT.isAndroid())) {
// clang-format off
static const struct {
const RTLIB::Libcall Op;
@@ -712,7 +714,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// The half <-> float conversion functions are always soft-float on
// non-watchos platforms, but are needed for some targets which use a
// hard-float calling convention by default.
- if (!Subtarget->isTargetWatchABI()) {
+ if (!TT.isWatchABI()) {
if (TM.isAAPCS_ABI()) {
setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
@@ -726,7 +728,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
// a __gnu_ prefix (which is the default).
- if (Subtarget->isTargetAEABI()) {
+ if (TT.isTargetAEABI()) {
static const struct {
const RTLIB::Libcall Op;
const char * const Name;
@@ -741,7 +743,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setLibcallName(LC.Op, LC.Name);
setLibcallCallingConv(LC.Op, LC.CC);
}
- } else if (!Subtarget->isTargetMachO()) {
+ } else if (!TT.isOSBinFormatMachO()) {
setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
}
@@ -1227,7 +1229,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::UDIV, MVT::i32, LibCall);
}
- if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
+ if (TT.isOSWindows() && !Subtarget->hasDivideInThumbMode()) {
setOperationAction(ISD::SDIV, MVT::i32, Custom);
setOperationAction(ISD::UDIV, MVT::i32, Custom);
@@ -1239,9 +1241,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::UREM, MVT::i32, Expand);
// Register based DivRem for AEABI (RTABI 4.2)
- if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
- Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
- Subtarget->isTargetWindows()) {
+ if (TT.isTargetAEABI() || TT.isAndroid() || TT.isTargetGNUAEABI() ||
+ TT.isTargetMuslAEABI() || TT.isOSWindows()) {
setOperationAction(ISD::SREM, MVT::i64, Custom);
setOperationAction(ISD::UREM, MVT::i64, Custom);
HasStandaloneRem = false;
@@ -1271,7 +1272,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
- if (Subtarget->isTargetWindows())
+ if (TT.isOSWindows())
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
else
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
@@ -1326,8 +1327,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
}
// Compute supported atomic widths.
- if (Subtarget->isTargetLinux() ||
- (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {
+ if (TT.isOSLinux() || (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {
// For targets where __sync_* routines are reliably available, we use them
// if necessary.
//
@@ -1538,7 +1538,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
// On MSVC, both 32-bit and 64-bit, ldexpf(f32) is not defined. MinGW has
// it, but it's just a wrapper around ldexp.
- if (Subtarget->isTargetWindows()) {
+ if (TT.isOSWindows()) {
for (ISD::NodeType Op : {ISD::FLDEXP, ISD::STRICT_FLDEXP, ISD::FFREXP})
if (isOperationExpand(Op, MVT::f32))
setOperationAction(Op, MVT::f32, Promote);
>From 9a79416929601a70db582efa8748d187cdc40efc Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Thu, 19 Jun 2025 10:05:56 +0900
Subject: [PATCH 2/2] Add comment
---
llvm/lib/Target/ARM/ARMSubtarget.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h
b/llvm/lib/Target/ARM/ARMSubtarget.h
index 7893796e313b7..03c405e60b67d 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -334,6 +334,8 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
const Triple &getTargetTriple() const { return TargetTriple; }
+ /// @{
+ /// These properties are per-module, please use the TargetMachine
TargetTriple.
bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
bool isTargetIOS() const { return TargetTriple.isiOS(); }
bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
@@ -359,6 +361,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
bool isTargetEHABICompatible() const {
return TargetTriple.isTargetEHABICompatible();
}
+ /// @}
bool isReadTPSoft() const {
return !(isReadTPTPIDRURW() || isReadTPTPIDRURO() || isReadTPTPIDRPRW());
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