llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: None (llvmbot) <details> <summary>Changes</summary> Backport 1db9eb23209826d9e799e68a9a4090f0328bf70c Requested by: @<!-- -->topperc --- Full diff: https://github.com/llvm/llvm-project/pull/149352.diff 3 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+16-16) - (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.h (+2-1) - (added) llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir (+198) ``````````diff diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index a796c910bd449..6c8e3da80b932 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -738,7 +738,8 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, MachineFunction &MF, uint64_t Offset, uint64_t RealStackSize, bool EmitCFI, bool NeedProbe, uint64_t ProbeSize, - bool DynAllocation) const { + bool DynAllocation, + MachineInstr::MIFlag Flag) const { DebugLoc DL; const RISCVRegisterInfo *RI = STI.getRegisterInfo(); const RISCVInstrInfo *TII = STI.getInstrInfo(); @@ -748,7 +749,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, // Simply allocate the stack if it's not big enough to require a probe. if (!NeedProbe || Offset <= ProbeSize) { RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-Offset), - MachineInstr::FrameSetup, getStackAlign()); + Flag, getStackAlign()); if (EmitCFI) CFIBuilder.buildDefCFAOffset(RealStackSize); @@ -759,7 +760,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, .addReg(RISCV::X0) .addReg(SPReg) .addImm(0) - .setMIFlags(MachineInstr::FrameSetup); + .setMIFlags(Flag); } return; @@ -770,14 +771,13 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, uint64_t CurrentOffset = 0; while (CurrentOffset + ProbeSize <= Offset) { RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, - StackOffset::getFixed(-ProbeSize), MachineInstr::FrameSetup, - getStackAlign()); + StackOffset::getFixed(-ProbeSize), Flag, getStackAlign()); // s[d|w] zero, 0(sp) BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) .addReg(RISCV::X0) .addReg(SPReg) .addImm(0) - .setMIFlags(MachineInstr::FrameSetup); + .setMIFlags(Flag); CurrentOffset += ProbeSize; if (EmitCFI) @@ -787,8 +787,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, uint64_t Residual = Offset - CurrentOffset; if (Residual) { RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, - StackOffset::getFixed(-Residual), MachineInstr::FrameSetup, - getStackAlign()); + StackOffset::getFixed(-Residual), Flag, getStackAlign()); if (EmitCFI) CFIBuilder.buildDefCFAOffset(Offset); @@ -798,7 +797,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, .addReg(RISCV::X0) .addReg(SPReg) .addImm(0) - .setMIFlags(MachineInstr::FrameSetup); + .setMIFlags(Flag); } } @@ -812,8 +811,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, Register TargetReg = RISCV::X6; // SUB TargetReg, SP, RoundedSize RI->adjustReg(MBB, MBBI, DL, TargetReg, SPReg, - StackOffset::getFixed(-RoundedSize), MachineInstr::FrameSetup, - getStackAlign()); + StackOffset::getFixed(-RoundedSize), Flag, getStackAlign()); if (EmitCFI) { // Set the CFA register to TargetReg. @@ -830,14 +828,14 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, if (Residual) { RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-Residual), - MachineInstr::FrameSetup, getStackAlign()); + Flag, getStackAlign()); if (DynAllocation) { // s[d|w] zero, 0(sp) BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) .addReg(RISCV::X0) .addReg(SPReg) .addImm(0) - .setMIFlags(MachineInstr::FrameSetup); + .setMIFlags(Flag); } } @@ -1034,7 +1032,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, MF.getInfo<RISCVMachineFunctionInfo>()->hasDynamicAllocation(); if (StackSize != 0) allocateStack(MBB, MBBI, MF, StackSize, RealStackSize, /*EmitCFI=*/true, - NeedProbe, ProbeSize, DynAllocation); + NeedProbe, ProbeSize, DynAllocation, + MachineInstr::FrameSetup); // Save SiFive CLIC CSRs into Stack emitSiFiveCLICPreemptibleSaves(MF, MBB, MBBI, DL); @@ -1082,7 +1081,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, allocateStack(MBB, MBBI, MF, SecondSPAdjustAmount, getStackSizeWithRVVPadding(MF), !hasFP(MF), NeedProbe, - ProbeSize, DynAllocation); + ProbeSize, DynAllocation, MachineInstr::FrameSetup); } if (RVVStackSize) { @@ -1814,7 +1813,8 @@ MachineBasicBlock::iterator RISCVFrameLowering::eliminateCallFramePseudoInstr( bool DynAllocation = MF.getInfo<RISCVMachineFunctionInfo>()->hasDynamicAllocation(); allocateStack(MBB, MI, MF, -Amount, -Amount, !hasFP(MF), - /*NeedProbe=*/true, ProbeSize, DynAllocation); + /*NeedProbe=*/true, ProbeSize, DynAllocation, + MachineInstr::NoFlags); } else { const RISCVRegisterInfo &RI = *STI.getRegisterInfo(); RI.adjustReg(MBB, MI, DL, SPReg, SPReg, StackOffset::getFixed(Amount), diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h index d013755ce58a0..6af63a4885f35 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -81,7 +81,8 @@ class RISCVFrameLowering : public TargetFrameLowering { void allocateStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineFunction &MF, uint64_t Offset, uint64_t RealStackSize, bool EmitCFI, bool NeedProbe, - uint64_t ProbeSize, bool DynAllocation) const; + uint64_t ProbeSize, bool DynAllocation, + MachineInstr::MIFlag Flag) const; protected: const RISCVSubtarget &STI; diff --git a/llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir b/llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir new file mode 100644 index 0000000000000..9ab7f41045c4d --- /dev/null +++ b/llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir @@ -0,0 +1,198 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \ +# RUN: | FileCheck %s -check-prefixes=RV64I +# RUN: llc -mtriple=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \ +# RUN: | FileCheck %s -check-prefixes=RV32I +--- | + ; Function Attrs: uwtable + define void @no_reserved_call_frame(i64 %n) #0 { + entry: + %v = alloca i32, i64 %n, align 4 + call void @callee_stack_args(ptr %v, [518 x i64] poison) + ret void + } + + declare void @callee_stack_args(ptr, [518 x i64]) #1 + + attributes #0 = { uwtable "frame-pointer"="none" "probe-stack"="inline-asm" "target-features"="+m" } + attributes #1 = { "target-features"="+m" } +... +--- +name: no_reserved_call_frame +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +noPhis: true +isSSA: false +noVRegs: true +hasFakeUses: false +callsEHReturn: false +callsUnwindInit: false +hasEHContTarget: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: true +registers: [] +liveins: + - { reg: '$x10', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: true + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + isCalleeSavedInfoValid: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: v, type: variable-sized, offset: 0, alignment: 1, stack-id: default, + callee-saved-register: '', callee-saved-restored: true, local-offset: 0, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + ; RV64I-LABEL: name: no_reserved_call_frame + ; RV64I: bb.0.entry: + ; RV64I-NEXT: successors: %bb.1(0x80000000) + ; RV64I-NEXT: liveins: $x10, $x1 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; RV64I-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; RV64I-NEXT: frame-setup SD killed $x1, $x2, 8 :: (store (s64) into %stack.1) + ; RV64I-NEXT: frame-setup SD killed $x8, $x2, 0 :: (store (s64) into %stack.2) + ; RV64I-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; RV64I-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; RV64I-NEXT: $x8 = frame-setup ADDI $x2, 16 + ; RV64I-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0 + ; RV64I-NEXT: renamable $x10 = SLLI killed renamable $x10, 2 + ; RV64I-NEXT: renamable $x10 = nuw ADDI killed renamable $x10, 15 + ; RV64I-NEXT: renamable $x10 = ANDI killed renamable $x10, -16 + ; RV64I-NEXT: renamable $x10 = SUB $x2, killed renamable $x10 + ; RV64I-NEXT: renamable $x11 = LUI 1 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.1.entry: + ; RV64I-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; RV64I-NEXT: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: $x2 = SUB $x2, renamable $x11 + ; RV64I-NEXT: SD $x0, $x2, 0 + ; RV64I-NEXT: BLT renamable $x10, $x2, %bb.1 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: bb.2.entry: + ; RV64I-NEXT: liveins: $x10 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: $x2 = ADDI renamable $x10, 0 + ; RV64I-NEXT: $x11 = LUI 1 + ; RV64I-NEXT: $x2 = SUB $x2, killed $x11 + ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_stack_args, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit undef $x11, implicit undef $x12, implicit undef $x13, implicit undef $x14, implicit undef $x15, implicit undef $x16, implicit undef $x17, implicit-def $x2 + ; RV64I-NEXT: $x10 = LUI 1 + ; RV64I-NEXT: $x2 = ADD $x2, killed $x10 + ; RV64I-NEXT: $x2 = frame-destroy ADDI $x8, -16 + ; RV64I-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 16 + ; RV64I-NEXT: $x1 = frame-destroy LD $x2, 8 :: (load (s64) from %stack.1) + ; RV64I-NEXT: $x8 = frame-destroy LD $x2, 0 :: (load (s64) from %stack.2) + ; RV64I-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; RV64I-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; RV64I-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; RV64I-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; RV64I-NEXT: PseudoRET + ; + ; RV32I-LABEL: name: no_reserved_call_frame + ; RV32I: bb.0.entry: + ; RV32I-NEXT: successors: %bb.1(0x80000000) + ; RV32I-NEXT: liveins: $x10, $x1 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; RV32I-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; RV32I-NEXT: frame-setup SW killed $x1, $x2, 12 :: (store (s32) into %stack.1) + ; RV32I-NEXT: frame-setup SW killed $x8, $x2, 8 :: (store (s32) into %stack.2) + ; RV32I-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; RV32I-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; RV32I-NEXT: $x8 = frame-setup ADDI $x2, 16 + ; RV32I-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0 + ; RV32I-NEXT: renamable $x10 = SLLI killed renamable $x10, 2 + ; RV32I-NEXT: renamable $x10 = nuw ADDI killed renamable $x10, 15 + ; RV32I-NEXT: renamable $x10 = ANDI killed renamable $x10, -16 + ; RV32I-NEXT: renamable $x10 = SUB $x2, killed renamable $x10 + ; RV32I-NEXT: renamable $x11 = LUI 1 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.1.entry: + ; RV32I-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; RV32I-NEXT: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: $x2 = SUB $x2, renamable $x11 + ; RV32I-NEXT: SD $x0, $x2, 0 + ; RV32I-NEXT: BLT renamable $x10, $x2, %bb.1 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: bb.2.entry: + ; RV32I-NEXT: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: $x2 = ADDI renamable $x10, 0 + ; RV32I-NEXT: $x11 = LUI 1 + ; RV32I-NEXT: $x2 = SUB $x2, killed $x11 + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_stack_args, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit undef $x11, implicit undef $x12, implicit undef $x13, implicit undef $x14, implicit undef $x15, implicit undef $x16, implicit undef $x17, implicit-def $x2 + ; RV32I-NEXT: $x10 = LUI 1 + ; RV32I-NEXT: $x2 = ADD $x2, killed $x10 + ; RV32I-NEXT: $x2 = frame-destroy ADDI $x8, -16 + ; RV32I-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 16 + ; RV32I-NEXT: $x1 = frame-destroy LW $x2, 12 :: (load (s32) from %stack.1) + ; RV32I-NEXT: $x8 = frame-destroy LW $x2, 8 :: (load (s32) from %stack.2) + ; RV32I-NEXT: frame-destroy CFI_INSTRUCTION restore $x1 + ; RV32I-NEXT: frame-destroy CFI_INSTRUCTION restore $x8 + ; RV32I-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; RV32I-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0 + ; RV32I-NEXT: PseudoRET + bb.0.entry: + successors: %bb.1(0x80000000) + liveins: $x10 + + renamable $x10 = SLLI killed renamable $x10, 2 + renamable $x10 = nuw ADDI killed renamable $x10, 15 + renamable $x10 = ANDI killed renamable $x10, -16 + renamable $x10 = SUB $x2, killed renamable $x10 + renamable $x11 = LUI 1 + + bb.1.entry: + successors: %bb.2(0x40000000), %bb.1(0x40000000) + liveins: $x10, $x11 + + $x2 = SUB $x2, renamable $x11 + SD $x0, $x2, 0 + BLT renamable $x10, $x2, %bb.1 + + bb.2.entry: + liveins: $x10 + + $x2 = ADDI renamable $x10, 0 + ADJCALLSTACKDOWN 4088, 0, implicit-def dead $x2, implicit $x2 + PseudoCALL target-flags(riscv-call) @callee_stack_args, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit undef $x11, implicit undef $x12, implicit undef $x13, implicit undef $x14, implicit undef $x15, implicit undef $x16, implicit undef $x17, implicit-def $x2 + ADJCALLSTACKUP 4088, 0, implicit-def dead $x2, implicit $x2 + PseudoRET +... `````````` </details> https://github.com/llvm/llvm-project/pull/149352 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
