llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-globalisel Author: Fabian Ritter (ritter-x2a) <details> <summary>Changes</summary> This flag applies to G_PTR_ADD instructions and indicates that the operation implements an inbounds getelementptr operation, i.e., the pointer operand is in bounds wrt. the allocated object it is based on, and the arithmetic does not change that. It is set when the IRTranslator lowers inbounds GEPs (currently only in some cases, to be extended with a future PR), and in the (build|materialize)ObjectPtrOffset functions. Inbounds information is useful in ISel when we have instructions that perform address computations whose intermediate steps must be in the same memory region as the final result. A follow-up patch will start using it for AMDGPU's flat memory instructions, where the immediate offset must not affect the memory aperture of the address. This is analogous to a concurrent effort in SDAG: #<!-- -->131862 (related: #<!-- -->140017, #<!-- -->141725). For SWDEV-516125. --- Patch is 4.78 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/150900.diff 92 Files Affected: - (modified) llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h (+3-3) - (modified) llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (+2-2) - (modified) llvm/include/llvm/CodeGen/MachineInstr.h (+3-1) - (modified) llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp (+5-2) - (modified) llvm/lib/CodeGen/MIRParser/MILexer.cpp (+1) - (modified) llvm/lib/CodeGen/MIRParser/MILexer.h (+1) - (modified) llvm/lib/CodeGen/MIRParser/MIParser.cpp (+4-1) - (modified) llvm/lib/CodeGen/MIRPrinter.cpp (+2) - (modified) llvm/lib/CodeGen/MachineInstr.cpp (+6) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll (+4-4) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll (+2-2) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (+41-41) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll (+24-24) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll (+1-1) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll (+1-1) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll (+8-8) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir (+16-16) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir (+40-40) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir (+24-24) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir (+11-11) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir (+2-2) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir (+12-12) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir (+3-3) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir (+8-8) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir (+4-4) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir (+1-1) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir (+1-1) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir (+2-2) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir (+5-5) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir (+24-24) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir (+16-16) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir (+12-12) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir (+4-4) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir (+4-4) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir (+5-5) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-vacopy.mir (+6-6) - (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir (+10-10) - (modified) llvm/test/CodeGen/AArch64/arm64-this-return.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll (+12-12) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll (+16-16) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll (+48-48) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll (+69-69) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll (+11-11) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir (+68-68) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir (+129-129) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir (+771-771) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir (+1362-1362) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir (+1393-1393) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir (+1975-1975) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir (+2495-2495) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir (+1060-1060) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir (+30-30) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll (+32-32) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir (+26-26) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir (+8-8) - (modified) llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll (+1-1) - (modified) llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir (+2-2) - (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll (+6-6) - (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll (+1-1) - (modified) llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll (+1-1) - (modified) llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memcpy.mir (+2-2) - (modified) llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir (+1-1) - (modified) llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir (+9-9) - (modified) llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir (+9-9) - (modified) llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir (+1-1) - (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll (+18-18) - (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll (+18-18) - (modified) llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll (+8-8) - (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir (+6-6) - (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir (+15-15) - (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir (+33-33) - (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir (+7-7) - (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir (+8-8) - (modified) llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir (+2-2) - (modified) llvm/test/CodeGen/X86/GlobalISel/legalize-undef.mir (+1-1) - (modified) llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll (+2-2) - (modified) llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll (+6-6) - (modified) llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp (+2-2) - (modified) llvm/utils/update_mir_test_checks.py (+1-1) ``````````diff diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h index 571ec6dd7e9ba..4292c0b31c750 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h @@ -26,9 +26,9 @@ namespace llvm { /// A base class for all GenericMachineInstrs. class GenericMachineInstr : public MachineInstr { - constexpr static unsigned PoisonFlags = NoUWrap | NoSWrap | NoUSWrap | - IsExact | Disjoint | NonNeg | - FmNoNans | FmNoInfs | SameSign; + constexpr static unsigned PoisonFlags = + NoUWrap | NoSWrap | NoUSWrap | IsExact | Disjoint | NonNeg | FmNoNans | + FmNoInfs | SameSign | InBounds; public: GenericMachineInstr() = delete; diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index 31f789ff04c15..99d3cd0aac85c 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -519,7 +519,7 @@ class LLVM_ABI MachineIRBuilder { std::optional<unsigned> Flags = std::nullopt); /// Build and insert an instruction with appropriate flags for addressing some - /// offset of an object, i.e.: \p Res = nuw G_PTR_ADD \p Op0, \p Op1 + /// offset of an object, i.e.: \p Res = nuw inbounds G_PTR_ADD \p Op0, \p Op1 /// The value of \p Op0 must be a pointer into or just after an object, adding /// the value of \p Op1 to it must yield to a pointer into or just after the /// same object. @@ -556,7 +556,7 @@ class LLVM_ABI MachineIRBuilder { /// Materialize and insert an instruction with appropriate flags for /// addressing some offset of an object, i.e.: - /// \p Res = nuw G_PTR_ADD \p Op0, (G_CONSTANT \p Value) + /// \p Res = nuw inbounds G_PTR_ADD \p Op0, (G_CONSTANT \p Value) /// The value of \p Op0 must be a pointer into or just after an object, adding /// \p Value to it must yield to a pointer into or just after the same object. /// diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h index 94d04b82666be..10a9b1ff1411d 100644 --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -122,7 +122,9 @@ class MachineInstr Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs. NoUSWrap = 1 << 20, // Instruction supports geps // no unsigned signed wrap. - SameSign = 1 << 21 // Both operands have the same sign. + SameSign = 1 << 21, // Both operands have the same sign. + InBounds = 1 << 22 // Pointer arithmetic remains inbounds. + // Implies NoUSWrap. }; private: diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 9aa8debd69227..27df7e369436a 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -211,7 +211,9 @@ MachineIRBuilder::buildPtrAdd(const DstOp &Res, const SrcOp &Op0, MachineInstrBuilder MachineIRBuilder::buildObjectPtrOffset(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1) { - return buildPtrAdd(Res, Op0, Op1, MachineInstr::MIFlag::NoUWrap); + return buildPtrAdd(Res, Op0, Op1, + MachineInstr::MIFlag::NoUWrap | + MachineInstr::MIFlag::InBounds); } std::optional<MachineInstrBuilder> @@ -234,7 +236,8 @@ MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0, std::optional<MachineInstrBuilder> MachineIRBuilder::materializeObjectPtrOffset( Register &Res, Register Op0, const LLT ValueTy, uint64_t Value) { return materializePtrAdd(Res, Op0, ValueTy, Value, - MachineInstr::MIFlag::NoUWrap); + MachineInstr::MIFlag::NoUWrap | + MachineInstr::MIFlag::InBounds); } MachineInstrBuilder MachineIRBuilder::buildMaskLowPtrBits(const DstOp &Res, diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp index 7153902fe2e7a..361cd19ee6941 100644 --- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp +++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp @@ -217,6 +217,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) { .Case("nneg", MIToken::kw_nneg) .Case("disjoint", MIToken::kw_disjoint) .Case("samesign", MIToken::kw_samesign) + .Case("inbounds", MIToken::kw_inbounds) .Case("nofpexcept", MIToken::kw_nofpexcept) .Case("unpredictable", MIToken::kw_unpredictable) .Case("debug-location", MIToken::kw_debug_location) diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h index d7cd06759cfbb..0e111d9292a2b 100644 --- a/llvm/lib/CodeGen/MIRParser/MILexer.h +++ b/llvm/lib/CodeGen/MIRParser/MILexer.h @@ -78,6 +78,7 @@ struct MIToken { kw_nneg, kw_disjoint, kw_samesign, + kw_inbounds, kw_debug_location, kw_debug_instr_number, kw_dbg_instr_ref, diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 3a364d5ff0d20..7f6745173f346 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -1477,7 +1477,8 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) { Token.is(MIToken::kw_nneg) || Token.is(MIToken::kw_disjoint) || Token.is(MIToken::kw_nusw) || - Token.is(MIToken::kw_samesign)) { + Token.is(MIToken::kw_samesign) || + Token.is(MIToken::kw_inbounds)) { // clang-format on // Mine frame and fast math flags if (Token.is(MIToken::kw_frame_setup)) @@ -1518,6 +1519,8 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) { Flags |= MachineInstr::NoUSWrap; if (Token.is(MIToken::kw_samesign)) Flags |= MachineInstr::SameSign; + if (Token.is(MIToken::kw_inbounds)) + Flags |= MachineInstr::InBounds; lex(); } diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index bc4e2999b750a..5c65cc08304b8 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -814,6 +814,8 @@ static void printMI(raw_ostream &OS, MFPrintState &State, OS << "nusw "; if (MI.getFlag(MachineInstr::SameSign)) OS << "samesign "; + if (MI.getFlag(MachineInstr::InBounds)) + OS << "inbounds "; // NOTE: Please add new MIFlags also to the MI_FLAGS_STR in // llvm/utils/update_mir_test_checks.py. diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index da3665b3b6a0b..79047f732808a 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -585,6 +585,8 @@ uint32_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) { MIFlags |= MachineInstr::MIFlag::NoUSWrap; if (GEP->hasNoUnsignedWrap()) MIFlags |= MachineInstr::MIFlag::NoUWrap; + if (GEP->isInBounds()) + MIFlags |= MachineInstr::MIFlag::InBounds; } // Copy the nonneg flag. @@ -1860,8 +1862,12 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, OS << "nneg "; if (getFlag(MachineInstr::Disjoint)) OS << "disjoint "; + if (getFlag(MachineInstr::NoUSWrap)) + OS << "nusw "; if (getFlag(MachineInstr::SameSign)) OS << "samesign "; + if (getFlag(MachineInstr::InBounds)) + OS << "inbounds "; // Print the opcode name. if (TII) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll index f0d9aa4dcd25d..639b6fd6cacc0 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll @@ -20,8 +20,8 @@ define i32 @cse_gep(ptr %ptr, i32 %idx) { ; O0-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]] ; O0-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL1]](s64) ; O0-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; O0-NEXT: %11:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD1]], [[C1]](s64) - ; O0-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD %11(p0) :: (load (s32) from %ir.gep2) + ; O0-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD1]], [[C1]](s64) + ; O0-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.gep2) ; O0-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]] ; O0-NEXT: $w0 = COPY [[ADD]](s32) ; O0-NEXT: RET_ReallyLR implicit $w0 @@ -39,8 +39,8 @@ define i32 @cse_gep(ptr %ptr, i32 %idx) { ; O3-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0) ; O3-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.gep1) ; O3-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; O3-NEXT: %9:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD]], [[C1]](s64) - ; O3-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD %9(p0) :: (load (s32) from %ir.gep2) + ; O3-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C1]](s64) + ; O3-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32) from %ir.gep2) ; O3-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[LOAD1]] ; O3-NEXT: $w0 = COPY [[ADD]](s32) ; O3-NEXT: RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll index 3b12885923db6..79b2e2eabe89c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll @@ -795,8 +795,8 @@ define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) { ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[PHI]], [[C111]] ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[MUL]](s64) ; CHECK-NEXT: [[C112:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 - ; CHECK-NEXT: %120:_(p0) = nuw nusw G_PTR_ADD [[PTR_ADD]], [[C112]](s64) - ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD %120(p0) :: (load (p0) from %ir.tmp59) + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw nusw inbounds G_PTR_ADD [[PTR_ADD]], [[C112]](s64) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD1]](p0) :: (load (p0) from %ir.tmp59) ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp ; CHECK-NEXT: $x0 = COPY [[COPY]](p0) ; CHECK-NEXT: $x1 = COPY [[LOAD]](p0) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 511536832278c..675c953fb1a84 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -599,10 +599,10 @@ define ptr @test_constant_null() { ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[VAL1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4) ; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 -; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[ADDR]], [[CST1]](s64) +; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](s64) ; CHECK: [[VAL2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load (s32) from %ir.addr + 4) ; CHECK: G_STORE [[VAL1]](s8), [[ADDR]](p0) :: (store (s8) into %ir.addr, align 4) -; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[ADDR]], [[CST1]](s64) +; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](s64) ; CHECK: G_STORE [[VAL2]](s32), [[GEP2]](p0) :: (store (s32) into %ir.addr + 4) define void @test_struct_memops(ptr %addr) { %val = load { i8, i32 }, ptr %addr @@ -706,7 +706,7 @@ define float @test_frem(float %arg1, float %arg2) { ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SADDO [[LHS]], [[RHS]] ; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr) ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 -; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[ADDR]], [[CST]](s64) +; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64) ; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4) declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) define void @test_sadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) { @@ -722,7 +722,7 @@ define void @test_sadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) { ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UADDO [[LHS]], [[RHS]] ; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr) ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 -; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[ADDR]], [[CST]](s64) +; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64) ; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4) declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) define void @test_uadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) { @@ -738,7 +738,7 @@ define void @test_uadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) { ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SSUBO [[LHS]], [[RHS]] ; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.subr) ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 -; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[ADDR]], [[CST]](s64) +; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64) ; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.subr + 4, align 4) declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) define void @test_ssub_overflow(i32 %lhs, i32 %rhs, ptr %subr) { @@ -754,7 +754,7 @@ define void @test_ssub_overflow(i32 %lhs, i32 %rhs, ptr %subr) { ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_USUBO [[LHS]], [[RHS]] ; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.subr) ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 -; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[ADDR]], [[CST]](s64) +; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64) ; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.subr + 4, align 4) declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) define void @test_usub_overflow(i32 %lhs, i32 %rhs, ptr %subr) { @@ -770,7 +770,7 @@ define void @test_usub_overflow(i32 %lhs, i32 %rhs, ptr %subr) { ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SMULO [[LHS]], [[RHS]] ; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr) ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 -; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[ADDR]], [[CST]](s64) +; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64) ; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4) declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) define void @test_smul_overflow(i32 %lhs, i32 %rhs, ptr %addr) { @@ -786,7 +786,7 @@ define void @test_smul_overflow(i32 %lhs, i32 %rhs, ptr %addr) { ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UMULO [[LHS]], [[RHS]] ; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr) ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 -; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[ADDR]], [[CST]](s64) +; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64) ; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4) declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32) define void @test_umul_overflow(i32 %lhs, i32 %rhs, ptr %addr) { @@ -799,13 +799,13 @@ define void @test_umul_overflow(i32 %lhs, i32 %rhs, ptr %addr) { ; CHECK: %0:_(p0) = COPY $x0 ; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4) ; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 -; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %0, [[CST1]](s64) +; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64) ; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load (s8) from %ir.addr + 4, align 4) ; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 -; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %0, [[CST2]](s64) +; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64) ; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 8) ; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12 -; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %0, [[CST3]](s64) +; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64) ; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 12) ; CHECK: $w0 = COPY [[LD3]](s32) %struct.nested = type {i8, { i8, i32 }, i32} @@ -820,16 +820,16 @@ define i32 @test_extractvalue(ptr %addr) { ; CHECK: %1:_(p0) = COPY $x1 ; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4) ; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 -; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %0, [[CST1]](s64) +; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64) ; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load (s8) from %ir.addr + 4, align 4) ; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 -; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %0, [[CST2]](s64) +; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64) ; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 8) ; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12 -; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %0, [[CST3]](s64) +; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64) ; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 12) ; CHECK: G_STORE [[LD2]](s8), %1(p0) :: (store (s8) into %ir.addr2, align 4) -; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %1, [[CST1]](s64) +; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %1, [[CST1]](s64) ; CHECK: G_STORE [[LD3]](s32), [[GEP4]](p0) :: (store (s32) into %ir.addr2 + 4) define void @test_extractvalue_agg(ptr %addr, ptr %addr2) { %struct = load %struct.nested, ptr %addr @@ -854,20 +854,20 @@ define void @test_trivial_extract_ptr([1 x ptr] %s, i8 %val) { ; CHECK: %1:_(s32) = COPY $w1 ; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4) ; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 -; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %0, [[CST1]](s64) +; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64) ; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load (s8) from %ir.addr + 4, align 4) ; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 -; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %0, [[CST2]](s64) +; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64) ; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 8) ; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12 -; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %0, [[CST3]](s64) +; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64) ; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 12) ; CHECK: G_STORE [[LD1]](s8), %0(p0) :: (store (s8) into %ir.addr, align 4) -; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %0, [[CST1]](s64) +; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64) ; CHECK: G_STORE [[LD2]](s8), [[GEP4]](p0) :: (store (s8) into %ir.addr + 4, align 4) -; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %0, [[CST2]](s64) +; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64) ; CHECK: G_STORE %1(s32), [[GEP5]](p0) :: (store (s32) into %ir.addr + 8) -; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw G_PTR_ADD %0, [[CST3]](s64) +; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64) ; CHECK: G_STORE [[LD4]](s32), [[GEP6]]... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/150900 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
