github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- 
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp 
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h 
llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.h 
--diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index c575714cf..339501cf7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1964,9 +1964,9 @@ bool 
AMDGPUInstructionSelector::selectDSGWSIntrinsic(MachineInstr &MI,
         return false;
 
       BuildMI(*MBB, &MI, DL, InstrDesc)
-        .addReg(VSrc)
-        .addImm(ImmOffset)
-        .cloneMemRefs(MI);
+          .addReg(VSrc)
+          .addImm(ImmOffset)
+          .cloneMemRefs(MI);
     } else {
       // Requires even register alignment, so create 64-bit value and pad the
       // top half with undef.
@@ -1977,20 +1977,18 @@ bool 
AMDGPUInstructionSelector::selectDSGWSIntrinsic(MachineInstr &MI,
       Register UndefReg = MRI->createVirtualRegister(SubRC);
       BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg);
       BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::REG_SEQUENCE), DataReg)
-        .addReg(VSrc)
-        .addImm(AMDGPU::sub0)
-        .addReg(UndefReg)
-        .addImm(AMDGPU::sub1);
+          .addReg(VSrc)
+          .addImm(AMDGPU::sub0)
+          .addReg(UndefReg)
+          .addImm(AMDGPU::sub1);
 
       BuildMI(*MBB, &MI, DL, InstrDesc)
-        .addReg(DataReg)
-        .addImm(ImmOffset)
-        .cloneMemRefs(MI);
+          .addReg(DataReg)
+          .addImm(ImmOffset)
+          .cloneMemRefs(MI);
     }
   } else {
-    BuildMI(*MBB, &MI, DL, InstrDesc)
-      .addImm(ImmOffset)
-      .cloneMemRefs(MI);
+    BuildMI(*MBB, &MI, DL, InstrDesc).addImm(ImmOffset).cloneMemRefs(MI);
   }
 
   MI.eraseFromParent();

``````````

</details>


https://github.com/llvm/llvm-project/pull/169373
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