llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Alexander Richardson (arichardson) <details> <summary>Changes</summary> After the latest change to tablegen, we now handle `RegClassByHwMode` correctly in the alias pattern output of -gen-asm-writer, so we can enable it for AMDGPU. Previously, `#define PRINT_ALIAS_INSTR` caused compilation failures due to tablegen referencing *RegClassID variables that do not exist for `RegClassByHwMode`. This causes a large number of test failures (380) so I just put this up as a draft pull request to see if it is desirable. It looks like the one test I updated uses wrong mnemonics so probably needs more work. --- Full diff: https://github.com/llvm/llvm-project/pull/171265.diff 3 Files Affected: - (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp (+3-1) - (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h (+5) - (modified) llvm/test/CodeGen/AMDGPU/max.ll (+4-4) ``````````diff diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index b63d71dc2fde9..35a61616b0f8c 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -44,7 +44,8 @@ void AMDGPUInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) { - printInstruction(MI, Address, STI, OS); + if (!PrintAliases || !printAliasInstr(MI, Address, STI, OS)) + printInstruction(MI, Address, STI, OS); printAnnotation(OS, Annot); } @@ -1944,4 +1945,5 @@ void AMDGPUInstPrinter::printScaleSel(const MCInst *MI, unsigned OpNo, O << " scale_sel:" << formatDec(Imm); } +#define PRINT_ALIAS_INSTR #include "AMDGPUGenAsmWriter.inc" diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h index 564d6eea52328..b851615280f89 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -39,6 +39,11 @@ class AMDGPUInstPrinter : public MCInstPrinter { raw_ostream &O, const MCRegisterInfo &MRI); private: + bool printAliasInstr(const MCInst *MI, uint64_t Address, + const MCSubtargetInfo &STI, raw_ostream &OS); + void printCustomAliasOperand(const MCInst *MI, uint64_t Address, + unsigned OpIdx, unsigned PrintMethodIdx, + const MCSubtargetInfo &STI, raw_ostream &OS); void printU16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); diff --git a/llvm/test/CodeGen/AMDGPU/max.ll b/llvm/test/CodeGen/AMDGPU/max.ll index ac6dd30283554..e839b3dc1a916 100644 --- a/llvm/test/CodeGen/AMDGPU/max.ll +++ b/llvm/test/CodeGen/AMDGPU/max.ll @@ -1120,7 +1120,7 @@ define amdgpu_kernel void @test_umax_ugt_i64(ptr addrspace(1) %out, i64 %a, i64 ; SI-NEXT: s_mov_b32 s4, s0 ; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v1, s9 -; SI-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1] +; SI-NEXT: V_CMP_GT_U64 vcc, s[2:3], v[0:1] ; SI-NEXT: s_mov_b32 s5, s1 ; SI-NEXT: s_and_b64 s[0:1], vcc, exec ; SI-NEXT: s_cselect_b32 s0, s3, s9 @@ -1174,7 +1174,7 @@ define amdgpu_kernel void @test_umax_uge_i64(ptr addrspace(1) %out, i64 %a, i64 ; SI-NEXT: s_mov_b32 s4, s0 ; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v1, s9 -; SI-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1] +; SI-NEXT: V_CMP_GE_U64 vcc, s[2:3], v[0:1] ; SI-NEXT: s_mov_b32 s5, s1 ; SI-NEXT: s_and_b64 s[0:1], vcc, exec ; SI-NEXT: s_cselect_b32 s0, s3, s9 @@ -1228,7 +1228,7 @@ define amdgpu_kernel void @test_imax_sgt_i64(ptr addrspace(1) %out, i64 %a, i64 ; SI-NEXT: s_mov_b32 s4, s0 ; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v1, s9 -; SI-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1] +; SI-NEXT: V_CMP_GT_I64 vcc, s[2:3], v[0:1] ; SI-NEXT: s_mov_b32 s5, s1 ; SI-NEXT: s_and_b64 s[0:1], vcc, exec ; SI-NEXT: s_cselect_b32 s0, s3, s9 @@ -1282,7 +1282,7 @@ define amdgpu_kernel void @test_imax_sge_i64(ptr addrspace(1) %out, i64 %a, i64 ; SI-NEXT: s_mov_b32 s4, s0 ; SI-NEXT: v_mov_b32_e32 v0, s8 ; SI-NEXT: v_mov_b32_e32 v1, s9 -; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1] +; SI-NEXT: V_CMP_GE_I64 vcc, s[2:3], v[0:1] ; SI-NEXT: s_mov_b32 s5, s1 ; SI-NEXT: s_and_b64 s[0:1], vcc, exec ; SI-NEXT: s_cselect_b32 s0, s3, s9 `````````` </details> https://github.com/llvm/llvm-project/pull/171265 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
