================
@@ -13,6 +13,58 @@ using namespace llvm;
#define DEBUG_TYPE "riscv-prera-sched-strategy"
+static cl::opt<bool> EnableVTypeSchedHeuristic(
+ "riscv-enable-vtype-sched-heuristic", cl::init(false), cl::Hidden,
+ cl::desc("Enable scheduling RVV instructions based on vtype heuristic "
+ "(pick instruction with compatible vtype first)"));
+
+RISCV::VSETVLIInfo
+RISCVPreRAMachineSchedStrategy::getVSETVLIInfo(const MachineInstr *MI) const {
+ unsigned TSFlags = MI->getDesc().TSFlags;
+ if (!RISCVII::hasSEWOp(TSFlags))
+ return RISCV::VSETVLIInfo();
+ return VIA.computeInfoForInstr(*MI);
+}
+
+bool RISCVPreRAMachineSchedStrategy::tryVType(RISCV::VSETVLIInfo TryVType,
+ RISCV::VSETVLIInfo CandVtype,
+ SchedCandidate &TryCand,
+ SchedCandidate &Cand,
+ CandReason Reason) const {
+ // Do not compare the vtype changes between top and bottom
+ // boundary.
+ if (Cand.AtTop != TryCand.AtTop)
+ return false;
+
+ // Try Cand first.
+ // We prefer the top node as it is straightforward from the perspective of
+ // vtype dataflow.
+ if (CandVtype.isValid() && TopVType.isValid() && Cand.AtTop &&
+ CandVtype == TopVType) {
----------------
mshockwave wrote:
remove braces, ditto for other places
https://github.com/llvm/llvm-project/pull/95924
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