github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- 
llvm/lib/Target/AMDGPU/SIISelLowering.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

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<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp 
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 362d25e3b..34e693569 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5864,8 +5864,10 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr 
&MI,
           .addReg(SrcReg)
           .addReg(FF1Reg);
       if (isFPOp) {
-        bool IsMinMaxOpc = Opc == AMDGPU::V_MIN_F32_e64 || Opc == 
AMDGPU::V_MAX_F32_e64;
-        bool NeedsNANCanonicalization = IsMinMaxOpc && (IsIEEEMode || 
IsGFX12Plus);
+        bool IsMinMaxOpc =
+            Opc == AMDGPU::V_MIN_F32_e64 || Opc == AMDGPU::V_MAX_F32_e64;
+        bool NeedsNANCanonicalization =
+            IsMinMaxOpc && (IsIEEEMode || IsGFX12Plus);
         Register LaneValVreg =
             MRI.createVirtualRegister(MRI.getRegClass(SrcReg));
         Register DstVreg = MRI.createVirtualRegister(MRI.getRegClass(SrcReg));

``````````

</details>


https://github.com/llvm/llvm-project/pull/175131
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