https://github.com/nhaehnle created https://github.com/llvm/llvm-project/pull/175844
This is a fairly mechanical change. Instead of returning true/false, we either keep the Infos vector empty or push one entry. --- **Stack**: - [4/4] #175846 - [3/4] #175845 - [2/4] #175844 ⬅ - [1/4] #175843 ⚠️ *Part of a stack created by [spr](https://github.com/nhaehnle/spr). Merging this PR using the GitHub UI may have unexpected results.* From 48931ab7e42f5e3d0f48df574ab3344d8b19d76f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= <[email protected]> Date: Mon, 12 Jan 2026 09:42:04 -0800 Subject: [PATCH] [CodeGen] Refactor targets to override the new getTgtMemIntrinsic overload (NFC) This is a fairly mechanical change. Instead of returning true/false, we either keep the Infos vector empty or push one entry. commit-id:c7770af6 --- .../Target/AArch64/AArch64ISelLowering.cpp | 58 ++++--- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 4 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 61 ++++--- llvm/lib/Target/AMDGPU/SIISelLowering.h | 2 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 58 ++++--- llvm/lib/Target/ARM/ARMISelLowering.h | 4 +- .../Target/Hexagon/HexagonISelLowering.cpp | 23 ++- llvm/lib/Target/Hexagon/HexagonISelLowering.h | 4 +- .../LoongArch/LoongArchISelLowering.cpp | 16 +- .../Target/LoongArch/LoongArchISelLowering.h | 4 +- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 152 ++++++++++++------ llvm/lib/Target/NVPTX/NVPTXISelLowering.h | 4 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 28 ++-- llvm/lib/Target/PowerPC/PPCISelLowering.h | 4 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 137 +++++++++------- llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 +- llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 13 +- llvm/lib/Target/SPIRV/SPIRVISelLowering.h | 4 +- .../WebAssembly/WebAssemblyISelLowering.cpp | 25 +-- .../WebAssembly/WebAssemblyISelLowering.h | 4 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 44 ++--- llvm/lib/Target/X86/X86ISelLowering.h | 12 +- 22 files changed, 397 insertions(+), 268 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 74ee8ff8ab5f5..2357ee42ea623 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -17349,7 +17349,7 @@ SDValue AArch64TargetLowering::LowerVSCALE(SDValue Op, /// Set the IntrinsicInfo for the `aarch64_sve_st<N>` intrinsics. template <unsigned NumVecs> -static bool +static void setInfoSVEStN(const AArch64TargetLowering &TLI, const DataLayout &DL, AArch64TargetLowering::IntrinsicInfo &Info, const CallBase &CI) { Info.opc = ISD::INTRINSIC_VOID; @@ -17369,24 +17369,29 @@ setInfoSVEStN(const AArch64TargetLowering &TLI, const DataLayout &DL, Info.offset = 0; Info.align.reset(); Info.flags = MachineMemOperand::MOStore; - return true; } /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment /// specified in the intrinsic calls. -bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void AArch64TargetLowering::getTgtMemIntrinsic( + SmallVectorImpl<IntrinsicInfo> &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; auto &DL = I.getDataLayout(); switch (Intrinsic) { case Intrinsic::aarch64_sve_st2: - return setInfoSVEStN<2>(*this, DL, Info, I); + setInfoSVEStN<2>(*this, DL, Info, I); + Infos.push_back(Info); + return; case Intrinsic::aarch64_sve_st3: - return setInfoSVEStN<3>(*this, DL, Info, I); + setInfoSVEStN<3>(*this, DL, Info, I); + Infos.push_back(Info); + return; case Intrinsic::aarch64_sve_st4: - return setInfoSVEStN<4>(*this, DL, Info, I); + setInfoSVEStN<4>(*this, DL, Info, I); + Infos.push_back(Info); + return; case Intrinsic::aarch64_neon_ld2: case Intrinsic::aarch64_neon_ld3: case Intrinsic::aarch64_neon_ld4: @@ -17401,7 +17406,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align.reset(); // volatile loads with NEON intrinsics not supported Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_neon_ld2lane: case Intrinsic::aarch64_neon_ld3lane: @@ -17422,7 +17428,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align.reset(); // volatile loads with NEON intrinsics not supported Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_neon_st2: case Intrinsic::aarch64_neon_st3: @@ -17444,7 +17451,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align.reset(); // volatile stores with NEON intrinsics not supported Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_neon_st2lane: case Intrinsic::aarch64_neon_st3lane: @@ -17468,7 +17476,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align.reset(); // volatile stores with NEON intrinsics not supported Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_ldaxr: case Intrinsic::aarch64_ldxr: { @@ -17479,7 +17488,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(ValTy); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_stlxr: case Intrinsic::aarch64_stxr: { @@ -17490,7 +17500,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(ValTy); Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_ldaxp: case Intrinsic::aarch64_ldxp: @@ -17500,7 +17511,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(16); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::aarch64_stlxp: case Intrinsic::aarch64_stxp: Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -17509,7 +17521,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(16); Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::aarch64_sve_ldnt1: { Type *ElTy = cast<VectorType>(I.getType())->getElementType(); Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -17518,7 +17531,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(ElTy); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MONonTemporal; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_sve_stnt1: { Type *ElTy = @@ -17529,7 +17543,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(ElTy); Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MONonTemporal; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_mops_memset_tag: { Value *Dst = I.getArgOperand(0); @@ -17542,13 +17557,12 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags = MachineMemOperand::MOStore; // The size of the memory being operated on is unknown at this point Info.size = MemoryLocation::UnknownSize; - return true; + Infos.push_back(Info); + return; } default: break; } - - return false; } bool AArch64TargetLowering::shouldReduceLoadWidth( diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 258651261fd62..db47de77bd39b 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -206,8 +206,8 @@ class AArch64TargetLowering : public TargetLowering { EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT, diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 139e2d101a077..cc239752cd453 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1328,10 +1328,11 @@ static void getCoopAtomicOperandsInfo(const CallBase &CI, bool IsLoad, Info.ssid = CI.getContext().getOrInsertSyncScopeID(Scope); } -bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, +void SITargetLowering::getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos, const CallBase &CI, MachineFunction &MF, unsigned IntrID) const { + IntrinsicInfo Info; Info.flags = MachineMemOperand::MONone; if (CI.hasMetadata(LLVMContext::MD_invariant_load)) Info.flags |= MachineMemOperand::MOInvariant; @@ -1345,7 +1346,7 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Intrinsic::getFnAttributes(CI.getContext(), (Intrinsic::ID)IntrID); MemoryEffects ME = Attr.getMemoryEffects(); if (ME.doesNotAccessMemory()) - return false; + return; // TODO: Should images get their own address space? Info.fallbackAddressSpace = AMDGPUAS::BUFFER_RESOURCE; @@ -1441,7 +1442,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, unsigned Width = cast<ConstantInt>(CI.getArgOperand(2))->getZExtValue(); Info.memVT = EVT::getIntegerVT(CI.getContext(), Width * 8); Info.ptrVal = CI.getArgOperand(1); - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_raw_atomic_buffer_load: case Intrinsic::amdgcn_raw_ptr_atomic_buffer_load: @@ -1451,11 +1453,13 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, memVTFromLoadIntrReturn(*this, MF.getDataLayout(), CI.getType(), std::numeric_limits<unsigned>::max()); Info.flags &= ~MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } } } - return true; + Infos.push_back(Info); + return; } switch (IntrID) { @@ -1471,7 +1475,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, if (!Vol->isZero()) Info.flags |= MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_ds_add_gs_reg_rtn: case Intrinsic::amdgcn_ds_sub_gs_reg_rtn: { @@ -1480,7 +1485,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.ptrVal = nullptr; Info.fallbackAddressSpace = AMDGPUAS::STREAMOUT_REGISTER; Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_ds_append: case Intrinsic::amdgcn_ds_consume: { @@ -1494,7 +1500,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, if (!Vol->isZero()) Info.flags |= MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_ds_atomic_async_barrier_arrive_b64: case Intrinsic::amdgcn_ds_atomic_barrier_arrive_rtn_b64: { @@ -1507,7 +1514,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.size = 8; Info.align.reset(); Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_image_bvh_dual_intersect_ray: case Intrinsic::amdgcn_image_bvh_intersect_ray: @@ -1523,7 +1531,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align.reset(); Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_global_atomic_fmin_num: case Intrinsic::amdgcn_global_atomic_fmax_num: @@ -1537,7 +1546,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MODereferenceable | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_flat_load_monitor_b32: case Intrinsic::amdgcn_flat_load_monitor_b64: @@ -1565,7 +1575,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.ptrVal = CI.getOperand(0); Info.align.reset(); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_cooperative_atomic_load_32x4B: case Intrinsic::amdgcn_cooperative_atomic_load_16x8B: @@ -1575,7 +1586,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.ptrVal = CI.getOperand(0); Info.align.reset(); getCoopAtomicOperandsInfo(CI, /*IsLoad=*/true, Info); - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_cooperative_atomic_store_32x4B: case Intrinsic::amdgcn_cooperative_atomic_store_16x8B: @@ -1585,7 +1597,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.ptrVal = CI.getArgOperand(0); Info.align.reset(); getCoopAtomicOperandsInfo(CI, /*IsLoad=*/false, Info); - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_ds_gws_init: case Intrinsic::amdgcn_ds_gws_barrier: @@ -1610,7 +1623,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags |= MachineMemOperand::MOLoad; else Info.flags |= MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_global_load_async_to_lds_b8: case Intrinsic::amdgcn_global_load_async_to_lds_b32: @@ -1624,7 +1638,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(CI.getContext(), getIntrMemWidth(IntrID)); Info.ptrVal = CI.getArgOperand(1); Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_global_store_async_from_lds_b8: case Intrinsic::amdgcn_global_store_async_from_lds_b32: @@ -1634,7 +1649,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(CI.getContext(), getIntrMemWidth(IntrID)); Info.ptrVal = CI.getArgOperand(0); Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_load_to_lds: case Intrinsic::amdgcn_global_load_lds: { @@ -1646,7 +1662,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, auto *Aux = cast<ConstantInt>(CI.getArgOperand(CI.arg_size() - 1)); if (Aux->getZExtValue() & AMDGPU::CPol::VOLATILE) Info.flags |= MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_ds_bvh_stack_rtn: case Intrinsic::amdgcn_ds_bvh_stack_push4_pop1_rtn: @@ -1666,7 +1683,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(4); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_s_prefetch_data: case Intrinsic::amdgcn_flat_prefetch: @@ -1675,10 +1693,11 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(CI.getContext(), 8); Info.ptrVal = CI.getArgOperand(0); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } default: - return false; + return; } } diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index e82f4528fcd09..c4020bdc7655c 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -336,7 +336,7 @@ class SITargetLowering final : public AMDGPUTargetLowering { MVT getPointerTy(const DataLayout &DL, unsigned AS) const override; MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &, const CallBase &, + void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &, const CallBase &, MachineFunction &MF, unsigned IntrinsicID) const override; diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 4fd845fbc07ac..0eaea492272e6 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -20680,10 +20680,10 @@ bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment /// specified in the intrinsic calls. -bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void ARMTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl<IntrinsicInfo> &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; switch (Intrinsic) { case Intrinsic::arm_neon_vld1: case Intrinsic::arm_neon_vld2: @@ -20706,7 +20706,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = cast<ConstantInt>(AlignArg)->getMaybeAlignValue(); // volatile loads with NEON intrinsics not supported Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_neon_vld1x2: case Intrinsic::arm_neon_vld1x3: @@ -20721,7 +20722,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = I.getParamAlign(I.arg_size() - 1).valueOrOne(); // volatile loads with NEON intrinsics not supported Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_neon_vst1: case Intrinsic::arm_neon_vst2: @@ -20747,7 +20749,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = cast<ConstantInt>(AlignArg)->getMaybeAlignValue(); // volatile stores with NEON intrinsics not supported Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_neon_vst1x2: case Intrinsic::arm_neon_vst1x3: @@ -20768,7 +20771,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = I.getParamAlign(0).valueOrOne(); // volatile stores with NEON intrinsics not supported Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vld2q: case Intrinsic::arm_mve_vld4q: { @@ -20782,7 +20786,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(VecTy->getScalarSizeInBits() / 8); // volatile loads with MVE intrinsics not supported Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vst2q: case Intrinsic::arm_mve_vst4q: { @@ -20796,7 +20801,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(VecTy->getScalarSizeInBits() / 8); // volatile stores with MVE intrinsics not supported Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vldr_gather_base: case Intrinsic::arm_mve_vldr_gather_base_predicated: { @@ -20805,7 +20811,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVT(I.getType()); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vldr_gather_base_wb: case Intrinsic::arm_mve_vldr_gather_base_wb_predicated: { @@ -20814,7 +20821,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVT(I.getType()->getContainedType(0)); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vldr_gather_offset: case Intrinsic::arm_mve_vldr_gather_offset_predicated: { @@ -20826,7 +20834,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, DataVT.getVectorNumElements()); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vstr_scatter_base: case Intrinsic::arm_mve_vstr_scatter_base_predicated: { @@ -20835,7 +20844,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVT(I.getArgOperand(2)->getType()); Info.align = Align(1); Info.flags |= MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vstr_scatter_base_wb: case Intrinsic::arm_mve_vstr_scatter_base_wb_predicated: { @@ -20844,7 +20854,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVT(I.getArgOperand(2)->getType()); Info.align = Align(1); Info.flags |= MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vstr_scatter_offset: case Intrinsic::arm_mve_vstr_scatter_offset_predicated: { @@ -20856,7 +20867,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, DataVT.getVectorNumElements()); Info.align = Align(1); Info.flags |= MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_ldaex: case Intrinsic::arm_ldrex: { @@ -20868,7 +20880,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(ValTy); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_stlex: case Intrinsic::arm_strex: { @@ -20880,7 +20893,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(ValTy); Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_stlexd: case Intrinsic::arm_strexd: @@ -20890,7 +20904,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(8); Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::arm_ldaexd: case Intrinsic::arm_ldrexd: @@ -20900,13 +20915,12 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(8); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; default: break; } - - return false; } /// Returns true if it is beneficial to convert a load of a constant diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index 6c07255ecb1a5..838ac71fd36c2 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -315,8 +315,8 @@ class VectorType; bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize = false) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; /// Returns true if it is beneficial to convert a load of a constant diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index e98d907350c2a..ebf0c5ce85e7d 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2026,13 +2026,12 @@ static Value *getUnderLyingObjectForBrevLdIntr(Value *V) { } /// Given an intrinsic, checks if on the target the intrinsic will need to map -/// to a MemIntrinsicNode (touches memory). If this is the case, it returns -/// true and store the intrinsic information into the IntrinsicInfo that was -/// passed to the function. -bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +/// to a MemIntrinsicNode (touches memory). If this is the case, it stores +/// the intrinsic information into the Infos vector. +void HexagonTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl<IntrinsicInfo> &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; switch (Intrinsic) { case Intrinsic::hexagon_L2_loadrd_pbr: case Intrinsic::hexagon_L2_loadri_pbr: @@ -2055,7 +2054,8 @@ bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(Info.memVT.getTypeForEVT(Cont)); Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::hexagon_V6_vgathermw: case Intrinsic::hexagon_V6_vgathermw_128B: @@ -2079,15 +2079,14 @@ bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = MaybeAlign(M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8); - Info.flags = MachineMemOperand::MOLoad | - MachineMemOperand::MOStore | + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } default: break; } - return false; } bool HexagonTargetLowering::hasBitTest(SDValue X, SDValue Y) const { diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index 3ef43ae7ad838..7f2d593db40c5 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -49,8 +49,8 @@ class HexagonTargetLowering : public TargetLowering { const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; bool isTruncateFree(Type *Ty1, Type *Ty2) const override; diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index 0d57a541f9eb2..d5d6c2da5ecc0 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -8914,17 +8914,17 @@ bool LoongArchTargetLowering::hasAndNot(SDValue Y) const { return VT.isScalarInteger() && !isa<ConstantSDNode>(Y); } -bool LoongArchTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void LoongArchTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl<IntrinsicInfo> &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { switch (Intrinsic) { default: - return false; + return; case Intrinsic::loongarch_masked_atomicrmw_xchg_i32: case Intrinsic::loongarch_masked_atomicrmw_add_i32: case Intrinsic::loongarch_masked_atomicrmw_sub_i32: - case Intrinsic::loongarch_masked_atomicrmw_nand_i32: + case Intrinsic::loongarch_masked_atomicrmw_nand_i32: { + IntrinsicInfo Info; Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::i32; Info.ptrVal = I.getArgOperand(0); @@ -8932,9 +8932,11 @@ bool LoongArchTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(4); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; // TODO: Add more Intrinsics later. } + } } // When -mlamcas is enabled, MinCmpXchgSizeInBits will be set to 8, diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h index f60ffb9d587c1..31f4b4cad7719 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h @@ -78,8 +78,8 @@ class LoongArchTargetLowering : public TargetLowering { Value *NewVal, Value *Mask, AtomicOrdering Ord) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index dfd9486b971be..692143f4b52ed 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -4107,13 +4107,13 @@ void NVPTXTargetLowering::LowerAsmOperandForConstraint( // because we need the information that is only available in the "Value" type // of destination // pointer. In particular, the address space information. -bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void NVPTXTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl<IntrinsicInfo> &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; switch (Intrinsic) { default: - return false; + return; case Intrinsic::nvvm_match_all_sync_i32p: case Intrinsic::nvvm_match_all_sync_i64p: Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -4124,7 +4124,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, // Our result depends on both our and other thread's arguments. Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_col: case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_row: case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_col_stride: @@ -4155,7 +4156,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m16n16k16_load_a_s8_col: case Intrinsic::nvvm_wmma_m16n16k16_load_a_s8_col_stride: @@ -4187,7 +4189,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(8); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m32n8k16_load_a_s8_col: @@ -4236,7 +4239,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m32n8k16_load_b_s8_col: @@ -4278,7 +4282,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(4); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_col: @@ -4299,7 +4304,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_col: @@ -4324,7 +4330,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m32n8k16_load_a_bf16_col: @@ -4355,7 +4362,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m8n8k128_load_c_s32_col: @@ -4379,7 +4387,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(8); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m8n8k4_load_a_f64_col: @@ -4397,7 +4406,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(8); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m8n8k4_load_c_f64_col: @@ -4410,7 +4420,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_col: @@ -4431,7 +4442,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_col: @@ -4456,7 +4468,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m16n16k16_store_d_s32_col: @@ -4477,7 +4490,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m8n8k128_store_d_s32_col: @@ -4497,7 +4511,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(8); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m8n8k4_store_d_f64_col: @@ -4510,7 +4525,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_stmatrix_sync_aligned_m8n8_x1_b16: @@ -4522,7 +4538,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(4); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_stmatrix_sync_aligned_m8n8_x4_b16: @@ -4534,7 +4551,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_atomic_add_gen_f_cta: @@ -4566,7 +4584,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_prefetch_tensormap: { @@ -4578,7 +4597,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tensormap_replace_global_address: @@ -4589,7 +4609,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tensormap_replace_rank: @@ -4607,7 +4628,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_ldu_global_i: @@ -4620,7 +4642,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags = MachineMemOperand::MOLoad; Info.align = cast<ConstantInt>(I.getArgOperand(1))->getMaybeAlignValue(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tex_1d_v4f32_s32: case Intrinsic::nvvm_tex_1d_v4f32_f32: @@ -4686,7 +4709,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_tex_1d_v4s32_s32: case Intrinsic::nvvm_tex_1d_v4s32_f32: @@ -4810,7 +4834,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_suld_1d_i8_clamp: case Intrinsic::nvvm_suld_1d_v2i8_clamp: @@ -4863,7 +4888,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_suld_1d_i16_clamp: case Intrinsic::nvvm_suld_1d_v2i16_clamp: @@ -4916,7 +4942,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_suld_1d_i32_clamp: case Intrinsic::nvvm_suld_1d_v2i32_clamp: @@ -4969,7 +4996,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_suld_1d_i64_clamp: case Intrinsic::nvvm_suld_1d_v2i64_clamp: @@ -5007,7 +5035,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_tcgen05_ld_16x64b_x1: case Intrinsic::nvvm_tcgen05_ld_32x32b_x1: @@ -5018,7 +5047,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x2: @@ -5031,7 +5061,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x4: @@ -5045,7 +5076,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x8: @@ -5059,7 +5091,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x16: @@ -5073,7 +5106,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x32: @@ -5087,7 +5121,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x64: @@ -5101,7 +5136,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x128: @@ -5115,7 +5151,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x1: @@ -5127,7 +5164,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x2: @@ -5140,7 +5178,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x4: @@ -5154,7 +5193,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x8: @@ -5168,7 +5208,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x16: @@ -5182,7 +5223,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x32: @@ -5196,7 +5238,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x64: @@ -5210,7 +5253,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x128: @@ -5224,7 +5268,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_mma_shared_disable_output_lane_cg1: case Intrinsic::nvvm_tcgen05_mma_shared_scale_d_disable_output_lane_cg1: @@ -5247,7 +5292,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_mma_shared_disable_output_lane_cg2: @@ -5271,10 +5317,10 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } } - return false; } /// getFunctionParamOptimizedAlign - since function arguments are passed via diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h index 33d62c28882a5..0ec49801a0155 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h @@ -32,8 +32,8 @@ class NVPTXTargetLowering : public TargetLowering { const NVPTXSubtarget &STI); SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; Align getFunctionArgumentAlignment(const Function *F, Type *Ty, unsigned Idx, diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index ef211bf8c8982..d51a28e6bf92e 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -18560,10 +18560,10 @@ PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { return false; } -bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void PPCTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl<IntrinsicInfo> &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; switch (Intrinsic) { case Intrinsic::ppc_atomicrmw_xchg_i128: case Intrinsic::ppc_atomicrmw_add_i128: @@ -18580,7 +18580,8 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(16); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::ppc_atomic_load_i128: Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::i128; @@ -18588,7 +18589,8 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(16); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::ppc_atomic_store_i128: Info.opc = ISD::INTRINSIC_VOID; Info.memVT = MVT::i128; @@ -18596,7 +18598,8 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(16); Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::ppc_altivec_lvx: case Intrinsic::ppc_altivec_lvxl: case Intrinsic::ppc_altivec_lvebx: @@ -18635,7 +18638,8 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.size = 2*VT.getStoreSize()-1; Info.align = Align(1); Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::ppc_altivec_stvx: case Intrinsic::ppc_altivec_stvxl: @@ -18675,7 +18679,8 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.size = 2*VT.getStoreSize()-1; Info.align = Align(1); Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::ppc_stdcx: case Intrinsic::ppc_stwcx: @@ -18706,13 +18711,12 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Alignment; Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } default: break; } - - return false; } /// It returns EVT::Other if the type should be determined using generic diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index daae839479c3c..935b307e50f69 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -492,8 +492,8 @@ namespace llvm { bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; /// It returns EVT::Other if the type should be determined using generic diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 03f1ceeba0209..654e5cb5d7e9a 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1936,10 +1936,10 @@ bool RISCVTargetLowering::shouldExpandCttzElements(EVT VT) const { VT.getVectorElementType() != MVT::i1 || !isTypeLegal(VT); } -bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void RISCVTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl<IntrinsicInfo> &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; auto &DL = I.getDataLayout(); auto SetRVVLoadStoreInfo = [&](unsigned PtrOp, bool IsStore, @@ -1980,7 +1980,7 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.size = MemoryLocation::UnknownSize; Info.flags |= IsStore ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); }; if (I.hasMetadata(LLVMContext::MD_nontemporal)) @@ -1989,7 +1989,7 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags |= RISCVTargetLowering::getTargetMMOFlags(I); switch (Intrinsic) { default: - return false; + return; case Intrinsic::riscv_masked_atomicrmw_xchg: case Intrinsic::riscv_masked_atomicrmw_add: case Intrinsic::riscv_masked_atomicrmw_sub: @@ -2011,7 +2011,8 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(4); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::riscv_seg2_load_mask: case Intrinsic::riscv_seg3_load_mask: case Intrinsic::riscv_seg4_load_mask: @@ -2026,8 +2027,9 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_sseg6_load_mask: case Intrinsic::riscv_sseg7_load_mask: case Intrinsic::riscv_sseg8_load_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ 0, /*IsStore*/ false, - /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ 0, /*IsStore*/ false, + /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + return; case Intrinsic::riscv_seg2_store_mask: case Intrinsic::riscv_seg3_store_mask: case Intrinsic::riscv_seg4_store_mask: @@ -2036,9 +2038,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_seg7_store_mask: case Intrinsic::riscv_seg8_store_mask: // Operands are (vec, ..., vec, ptr, mask, vl) - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3, - /*IsStore*/ true, - /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3, + /*IsStore*/ true, + /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + return; case Intrinsic::riscv_sseg2_store_mask: case Intrinsic::riscv_sseg3_store_mask: case Intrinsic::riscv_sseg4_store_mask: @@ -2047,47 +2050,53 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_sseg7_store_mask: case Intrinsic::riscv_sseg8_store_mask: // Operands are (vec, ..., vec, ptr, offset, mask, vl) - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, - /*IsStore*/ true, - /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, + /*IsStore*/ true, + /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + return; case Intrinsic::riscv_vlm: - return SetRVVLoadStoreInfo(/*PtrOp*/ 0, - /*IsStore*/ false, - /*IsUnitStrided*/ true, - /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ 0, + /*IsStore*/ false, + /*IsUnitStrided*/ true, + /*UsePtrVal*/ true); + return; case Intrinsic::riscv_vle: case Intrinsic::riscv_vle_mask: case Intrinsic::riscv_vleff: case Intrinsic::riscv_vleff_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ 1, - /*IsStore*/ false, - /*IsUnitStrided*/ true, - /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ 1, + /*IsStore*/ false, + /*IsUnitStrided*/ true, + /*UsePtrVal*/ true); + return; case Intrinsic::riscv_vsm: case Intrinsic::riscv_vse: case Intrinsic::riscv_vse_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ 1, - /*IsStore*/ true, - /*IsUnitStrided*/ true, - /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ 1, + /*IsStore*/ true, + /*IsUnitStrided*/ true, + /*UsePtrVal*/ true); + return; case Intrinsic::riscv_vlse: case Intrinsic::riscv_vlse_mask: case Intrinsic::riscv_vloxei: case Intrinsic::riscv_vloxei_mask: case Intrinsic::riscv_vluxei: case Intrinsic::riscv_vluxei_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ 1, - /*IsStore*/ false, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ 1, + /*IsStore*/ false, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vsse: case Intrinsic::riscv_vsse_mask: case Intrinsic::riscv_vsoxei: case Intrinsic::riscv_vsoxei_mask: case Intrinsic::riscv_vsuxei: case Intrinsic::riscv_vsuxei_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ 1, - /*IsStore*/ true, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ 1, + /*IsStore*/ true, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vlseg2: case Intrinsic::riscv_vlseg3: case Intrinsic::riscv_vlseg4: @@ -2102,9 +2111,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vlseg6ff: case Intrinsic::riscv_vlseg7ff: case Intrinsic::riscv_vlseg8ff: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3, - /*IsStore*/ false, - /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3, + /*IsStore*/ false, + /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + return; case Intrinsic::riscv_vlseg2_mask: case Intrinsic::riscv_vlseg3_mask: case Intrinsic::riscv_vlseg4_mask: @@ -2119,9 +2129,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vlseg6ff_mask: case Intrinsic::riscv_vlseg7ff_mask: case Intrinsic::riscv_vlseg8ff_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 5, - /*IsStore*/ false, - /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 5, + /*IsStore*/ false, + /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + return; case Intrinsic::riscv_vlsseg2: case Intrinsic::riscv_vlsseg3: case Intrinsic::riscv_vlsseg4: @@ -2143,9 +2154,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vluxseg6: case Intrinsic::riscv_vluxseg7: case Intrinsic::riscv_vluxseg8: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, - /*IsStore*/ false, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, + /*IsStore*/ false, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vlsseg2_mask: case Intrinsic::riscv_vlsseg3_mask: case Intrinsic::riscv_vlsseg4_mask: @@ -2167,9 +2179,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vluxseg6_mask: case Intrinsic::riscv_vluxseg7_mask: case Intrinsic::riscv_vluxseg8_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 6, - /*IsStore*/ false, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 6, + /*IsStore*/ false, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vsseg2: case Intrinsic::riscv_vsseg3: case Intrinsic::riscv_vsseg4: @@ -2177,9 +2190,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vsseg6: case Intrinsic::riscv_vsseg7: case Intrinsic::riscv_vsseg8: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3, - /*IsStore*/ true, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3, + /*IsStore*/ true, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vsseg2_mask: case Intrinsic::riscv_vsseg3_mask: case Intrinsic::riscv_vsseg4_mask: @@ -2187,9 +2201,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vsseg6_mask: case Intrinsic::riscv_vsseg7_mask: case Intrinsic::riscv_vsseg8_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, - /*IsStore*/ true, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, + /*IsStore*/ true, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vssseg2: case Intrinsic::riscv_vssseg3: case Intrinsic::riscv_vssseg4: @@ -2211,9 +2226,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vsuxseg6: case Intrinsic::riscv_vsuxseg7: case Intrinsic::riscv_vsuxseg8: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, - /*IsStore*/ true, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, + /*IsStore*/ true, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vssseg2_mask: case Intrinsic::riscv_vssseg3_mask: case Intrinsic::riscv_vssseg4_mask: @@ -2235,9 +2251,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vsuxseg6_mask: case Intrinsic::riscv_vsuxseg7_mask: case Intrinsic::riscv_vsuxseg8_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 5, - /*IsStore*/ true, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 5, + /*IsStore*/ true, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_sf_vlte8: case Intrinsic::riscv_sf_vlte16: case Intrinsic::riscv_sf_vlte32: @@ -2264,7 +2281,8 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, } Info.size = MemoryLocation::UnknownSize; Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::riscv_sf_vste8: case Intrinsic::riscv_sf_vste16: case Intrinsic::riscv_sf_vste32: @@ -2291,7 +2309,8 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, } Info.size = MemoryLocation::UnknownSize; Info.flags |= MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } } diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index fa164d400c245..decf54e6c8856 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -35,8 +35,8 @@ class RISCVTargetLowering : public TargetLowering { const RISCVSubtarget &getSubtarget() const { return Subtarget; } - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp index 36fa5fa9a70cb..3e5ce4b90ea4a 100644 --- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp @@ -93,10 +93,10 @@ MVT SPIRVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, return getRegisterType(Context, VT); } -bool SPIRVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void SPIRVTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl<IntrinsicInfo> &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; unsigned AlignIdx = 3; switch (Intrinsic) { case Intrinsic::spv_load: @@ -112,13 +112,12 @@ bool SPIRVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::i64; // TODO: take into account opaque pointers (don't use getElementType). // MVT::getVT(PtrTy->getElementType()); - return true; - break; + Infos.push_back(Info); + return; } default: break; } - return false; } std::pair<unsigned, const TargetRegisterClass *> diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h index 5746832c8fd95..462605ab6fe36 100644 --- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h +++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h @@ -48,8 +48,8 @@ class SPIRVTargetLowering : public TargetLowering { EVT VT) const override; MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; std::pair<unsigned, const TargetRegisterClass *> diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index a2557f45395c2..337186f854709 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -1063,10 +1063,10 @@ EVT WebAssemblyTargetLowering::getSetCCResultType(const DataLayout &DL, return EVT::getIntegerVT(C, 32); } -bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void WebAssemblyTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl<IntrinsicInfo> &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; switch (Intrinsic) { case Intrinsic::wasm_memory_atomic_notify: Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -1081,7 +1081,8 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, // instructions are treated as volatiles in the backend, so we should be // consistent. The same applies for wasm_atomic_wait intrinsics too. Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::wasm_memory_atomic_wait32: Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::i32; @@ -1089,7 +1090,8 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(4); Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::wasm_memory_atomic_wait64: Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::i64; @@ -1097,7 +1099,8 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(8); Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::wasm_loadf16_f32: Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::f16; @@ -1105,7 +1108,8 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(2); Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::wasm_storef16_f32: Info.opc = ISD::INTRINSIC_VOID; Info.memVT = MVT::f16; @@ -1113,9 +1117,10 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(2); Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; default: - return false; + return; } } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h index c37970f458e36..79763d0da0bda 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h @@ -58,8 +58,8 @@ class WebAssemblyTargetLowering final : public TargetLowering { bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a354704c5958b..ab02c0a1577ae 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -3138,10 +3138,10 @@ static bool useVPTERNLOG(const X86Subtarget &Subtarget, MVT VT) { VT.is512BitVector(); } -bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void X86TargetLowering::getTgtMemIntrinsic( + SmallVectorImpl<IntrinsicInfo> &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; Info.flags = MachineMemOperand::MONone; Info.offset = 0; @@ -3155,7 +3155,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 48); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::x86_aesenc256kl: case Intrinsic::x86_aesdec256kl: Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -3163,7 +3164,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 64); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::x86_aesencwide128kl: case Intrinsic::x86_aesdecwide128kl: Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -3171,7 +3173,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 48); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::x86_aesencwide256kl: case Intrinsic::x86_aesdecwide256kl: Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -3179,7 +3182,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 64); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::x86_cmpccxadd32: case Intrinsic::x86_cmpccxadd64: case Intrinsic::x86_atomic_bts: @@ -3192,7 +3196,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(Size); Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::x86_atomic_bts_rm: case Intrinsic::x86_atomic_btc_rm: @@ -3204,7 +3209,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(Size); Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::x86_aadd32: case Intrinsic::x86_aadd64: @@ -3226,10 +3232,11 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(Size); Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } } - return false; + return; } switch (IntrData->Type) { @@ -3250,7 +3257,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVectorVT(ScalarVT, VT.getVectorNumElements()); Info.align = Align(1); Info.flags |= MachineMemOperand::MOStore; - break; + Infos.push_back(Info); + return; } case GATHER: case GATHER_AVX2: { @@ -3263,7 +3271,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - break; + Infos.push_back(Info); + return; } case SCATTER: { Info.opc = ISD::INTRINSIC_VOID; @@ -3275,13 +3284,12 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts); Info.align = Align(1); Info.flags |= MachineMemOperand::MOStore; - break; + Infos.push_back(Info); + return; } default: - return false; + return; } - - return true; } /// Returns true if the target can instruction select the diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 7c8135d3a2013..dcd103ed052b0 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -1479,12 +1479,12 @@ namespace llvm { unsigned SelectOpcode, SDValue X, SDValue Y) const override; - /// Given an intrinsic, checks if on the target the intrinsic will need to map - /// to a MemIntrinsicNode (touches memory). If this is the case, it returns - /// true and stores the intrinsic information into the IntrinsicInfo that was - /// passed to the function. - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + /// Given an intrinsic, checks if on the target the intrinsic will need to + /// map to a MemIntrinsicNode (touches memory). If this is the case, it + /// returns true and stores the intrinsic information into the IntrinsicInfo + /// that was passed to the function. + void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; /// Returns true if the target can instruction select the _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
