================
@@ -727,6 +763,9 @@ static constexpr DecoderListEntry DecoderList32[]{
{DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
{DecoderTableXAIF32, XAIFGroup, "AI Foundry extensions"},
// Standard Extensions
+ {DecoderTableRVYOnly32,
+ {RISCV::FeatureStdExtY},
+ "RVY-only standard 32-bit instructions"},
----------------
arichardson wrote:
I agree we should not conflict with anything, but it was needed for `SRLIY`
(aka `YHIR`) which technically overlaps with RV64-SRLI for RV32Y. Not sure if
there is a more elegant way to solve this?
```
// The SRLIY instruction uses the encoding of SRLI with shamt==XLEN, other
// values are not supported. YHIR is a pseudo that expands to the correct
// shift value depending on RV32/RV64.
let DecoderNamespace = "RVYOnly", hasSideEffects = 0, mayLoad = 0,
mayStore = 0 in {
def SRLIY : RVInstIBase<0b101, OPC_OP_IMM, (outs GPR:$rd),
(ins YGPR:$rs1, uimm7_srliy:$shamt), "srliy",
"$rd, $rs1, $shamt"> {
bits<7> shamt;
let Inst{31 -27} = 0b00000;
let Inst{26 -20} = shamt;
}
}
let Predicates = [HasStdExtY, IsRV64] in {
def : InstAlias<"yhir $rd, $rs1", (SRLIY GPR:$rd, YGPR:$rs1, 64)>;
}
let Predicates = [HasStdExtY, IsRV32] in {
def : InstAlias<"yhir $rd, $rs1", (SRLIY GPR:$rd, YGPR:$rs1, 32)>;
}
```
https://github.com/llvm/llvm-project/pull/176871
_______________________________________________
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
