https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/176691
>From 678d33914a5f17cce84baf3f559b09f60995fc53 Mon Sep 17 00:00:00 2001 From: vikhegde <[email protected]> Date: Fri, 16 Jan 2026 14:34:55 +0530 Subject: [PATCH 1/2] [AMDGPU] Fix DomTree preservation in SILowerControlFlow when nodes are deleted --- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 5 ++ ...i-lower-control-flow-preserve-dom-tree.mir | 59 +++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp index bb912be85de74..9cc86e84407b1 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -744,6 +744,11 @@ bool SILowerControlFlow::removeMBBifRedundant(MachineBasicBlock &MBB) { if (PDT) PDT->applyUpdates(DTUpdates); + if (MDT && MDT->getNode(&MBB)) + MDT->eraseNode(&MBB); + if (PDT && PDT->getNode(&MBB)) + PDT->eraseNode(&MBB); + MBB.clear(); MBB.eraseFromParent(); if (FallThrough && !FallThrough->isLayoutSuccessor(Succ)) { diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir new file mode 100644 index 0000000000000..0760bdfee43d7 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir @@ -0,0 +1,59 @@ +# RUN: llc -o /dev/null -mcpu=gfx1201 -mtriple=amdgcn-amd-amdhsa -passes="require<machine-post-dom-tree>,si-lower-control-flow,print<machine-post-dom-tree>" %s 2>&1 | FileCheck %s + +# CHECK: Inorder PostDominator Tree: +# CHECK-NEXT: [1] <<exit node>> {4294967295,4294967295} [0] +# CHECK-NEXT: [2] %bb.4 {4294967295,4294967295} [1] +# CHECK-NEXT: [3] %bb.2 {4294967295,4294967295} [2] +# CHECK-NEXT: [3] %bb.0 {4294967295,4294967295} [2] +# CHECK-NEXT: [3] %bb.1 {4294967295,4294967295} [2] + +--- +name: preserve_dom_tree +body: | + bb.0.entry: + successors: %bb.1(0x40000000), %bb.4(0x40000000) + liveins: $vgpr0, $sgpr0_sgpr1, $ttmp9 + + %6:sreg_32 = COPY $ttmp9 + %5:sgpr_64(p4) = COPY killed $sgpr0_sgpr1 + %4:vgpr_32(s32) = COPY killed $vgpr0 + %0:sgpr_128 = S_LOAD_DWORDX4_IMM %5(p4), 0, 0 + %7:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed %5(p4), 28, 0 + %10:sreg_64_xexec_xnull = REG_SEQUENCE %0.sub2, %subreg.sub0, %0.sub3, %subreg.sub1 + %12:sreg_32 = S_AND_B32 killed %7, 65535, implicit-def dead $scc + %39:vreg_64 = REG_SEQUENCE killed %4(s32), %subreg.sub0, undef %40:vgpr_32, %subreg.sub1 + %16:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 killed %6, killed %12, killed %39, 0, implicit $exec + %20:vgpr_32 = GLOBAL_LOAD_UBYTE_SADDR killed %10, killed %16.sub0, 0, 0, implicit $exec + %21:vgpr_32 = V_AND_B32_e64 1, killed %20, implicit $exec + %22:sreg_32 = V_CMP_EQ_U32_e64 1, killed %21, implicit $exec + %1:sreg_32 = SI_IF killed %22, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + S_BRANCH %bb.1 + + bb.1: + successors: %bb.2(0x40000000), %bb.3(0x40000000) + + %23:sreg_32 = COPY $exec_lo + %25:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %23, 0, implicit $exec + %26:sreg_32 = V_CMP_EQ_U32_e64 0, killed %25, implicit $exec + %3:sreg_32 = SI_IF killed %26, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + S_BRANCH %bb.2 + + bb.2: + successors: %bb.3(0x80000000) + + %27:sreg_32 = S_BCNT1_I32_B32 killed %23, implicit-def dead $scc + %28:vgpr_32 = V_CVT_F32_UBYTE0_e64 killed %27, 0, 0, implicit $exec + %38:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 1092616192, 0, killed %28, 0, 0, implicit $mode, implicit $exec + %34:sreg_64_xexec_xnull = REG_SEQUENCE killed %0.sub0, %subreg.sub0, %0.sub1, %subreg.sub1 + %35:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + GLOBAL_ATOMIC_ADD_F32_SADDR killed %35, killed %38, killed %34, 0, 0, implicit $exec + + bb.3: + successors: %bb.4(0x80000000) + + SI_END_CF killed %3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + + bb.4: + SI_END_CF killed %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + S_ENDPGM 0 +... >From 654234073f6a7caca4f0b0f42e293a92b937172f Mon Sep 17 00:00:00 2001 From: vikhegde <[email protected]> Date: Tue, 20 Jan 2026 15:29:41 +0530 Subject: [PATCH 2/2] review comments --- ...i-lower-control-flow-preserve-dom-tree.mir | 68 ++++++++++--------- 1 file changed, 37 insertions(+), 31 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir index 0760bdfee43d7..1ef3d63a0496d 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir @@ -1,11 +1,17 @@ -# RUN: llc -o /dev/null -mcpu=gfx1201 -mtriple=amdgcn-amd-amdhsa -passes="require<machine-post-dom-tree>,si-lower-control-flow,print<machine-post-dom-tree>" %s 2>&1 | FileCheck %s +# RUN: llc -mcpu=gfx1201 -mtriple=amdgcn-amd-amdhsa -passes="require<machine-post-dom-tree>,require<machine-dom-tree>,si-lower-control-flow,print<machine-post-dom-tree>,print<machine-dom-tree>" -filetype=null %s 2>&1 | FileCheck %s # CHECK: Inorder PostDominator Tree: -# CHECK-NEXT: [1] <<exit node>> {4294967295,4294967295} [0] -# CHECK-NEXT: [2] %bb.4 {4294967295,4294967295} [1] -# CHECK-NEXT: [3] %bb.2 {4294967295,4294967295} [2] -# CHECK-NEXT: [3] %bb.0 {4294967295,4294967295} [2] -# CHECK-NEXT: [3] %bb.1 {4294967295,4294967295} [2] +# CHECK-NEXT: [1] <<exit node>> {4294967295,4294967295} [0] +# CHECK-NEXT: [2] %bb.4 {4294967295,4294967295} [1] +# CHECK-NEXT: [3] %bb.0 {4294967295,4294967295} [2] +# CHECK-NEXT: [3] %bb.1 {4294967295,4294967295} [2] +# CHECK-NEXT: [3] %bb.2 {4294967295,4294967295} [2] + +# CHECK: Inorder Dominator Tree: +# CHECK-NEXT: [1] %bb.0 {4294967295,4294967295} [0] +# CHECK-NEXT: [2] %bb.1 {4294967295,4294967295} [1] +# CHECK-NEXT: [3] %bb.2 {4294967295,4294967295} [2] +# CHECK-NEXT: [2] %bb.4 {4294967295,4294967295} [1] --- name: preserve_dom_tree @@ -14,46 +20,46 @@ body: | successors: %bb.1(0x40000000), %bb.4(0x40000000) liveins: $vgpr0, $sgpr0_sgpr1, $ttmp9 - %6:sreg_32 = COPY $ttmp9 - %5:sgpr_64(p4) = COPY killed $sgpr0_sgpr1 - %4:vgpr_32(s32) = COPY killed $vgpr0 - %0:sgpr_128 = S_LOAD_DWORDX4_IMM %5(p4), 0, 0 - %7:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed %5(p4), 28, 0 - %10:sreg_64_xexec_xnull = REG_SEQUENCE %0.sub2, %subreg.sub0, %0.sub3, %subreg.sub1 - %12:sreg_32 = S_AND_B32 killed %7, 65535, implicit-def dead $scc - %39:vreg_64 = REG_SEQUENCE killed %4(s32), %subreg.sub0, undef %40:vgpr_32, %subreg.sub1 - %16:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 killed %6, killed %12, killed %39, 0, implicit $exec - %20:vgpr_32 = GLOBAL_LOAD_UBYTE_SADDR killed %10, killed %16.sub0, 0, 0, implicit $exec - %21:vgpr_32 = V_AND_B32_e64 1, killed %20, implicit $exec - %22:sreg_32 = V_CMP_EQ_U32_e64 1, killed %21, implicit $exec - %1:sreg_32 = SI_IF killed %22, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + %0:sreg_32 = COPY $ttmp9 + %1:sgpr_64 = COPY killed $sgpr0_sgpr1 + %2:vgpr_32 = COPY killed $vgpr0 + %3:sgpr_128 = S_LOAD_DWORDX4_IMM %1, 0, 0 + %4:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed %1, 28, 0 + %5:sreg_64_xexec_xnull = REG_SEQUENCE %3.sub2, %subreg.sub0, %3.sub3, %subreg.sub1 + %6:sreg_32 = S_AND_B32 killed %4, 65535, implicit-def dead $scc + %7:vreg_64 = REG_SEQUENCE killed %2(s32), %subreg.sub0, undef %8:vgpr_32, %subreg.sub1 + %9:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 killed %0, killed %6, killed %7, 0, implicit $exec + %10:vgpr_32 = GLOBAL_LOAD_UBYTE_SADDR killed %5, killed %9.sub0, 0, 0, implicit $exec + %11:vgpr_32 = V_AND_B32_e64 1, killed %10, implicit $exec + %12:sreg_32 = V_CMP_EQ_U32_e64 1, killed %11, implicit $exec + %13:sreg_32 = SI_IF killed %12, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec S_BRANCH %bb.1 bb.1: successors: %bb.2(0x40000000), %bb.3(0x40000000) - %23:sreg_32 = COPY $exec_lo - %25:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %23, 0, implicit $exec - %26:sreg_32 = V_CMP_EQ_U32_e64 0, killed %25, implicit $exec - %3:sreg_32 = SI_IF killed %26, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + %14:sreg_32 = COPY $exec_lo + %15:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %14, 0, implicit $exec + %16:sreg_32 = V_CMP_EQ_U32_e64 0, killed %15, implicit $exec + %17:sreg_32 = SI_IF killed %16, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec S_BRANCH %bb.2 bb.2: successors: %bb.3(0x80000000) - %27:sreg_32 = S_BCNT1_I32_B32 killed %23, implicit-def dead $scc - %28:vgpr_32 = V_CVT_F32_UBYTE0_e64 killed %27, 0, 0, implicit $exec - %38:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 1092616192, 0, killed %28, 0, 0, implicit $mode, implicit $exec - %34:sreg_64_xexec_xnull = REG_SEQUENCE killed %0.sub0, %subreg.sub0, %0.sub1, %subreg.sub1 - %35:vgpr_32 = V_MOV_B32_e32 0, implicit $exec - GLOBAL_ATOMIC_ADD_F32_SADDR killed %35, killed %38, killed %34, 0, 0, implicit $exec + %18:sreg_32 = S_BCNT1_I32_B32 killed %14, implicit-def dead $scc + %19:vgpr_32 = V_CVT_F32_UBYTE0_e64 killed %18, 0, 0, implicit $exec + %20:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 1092616192, 0, killed %19, 0, 0, implicit $mode, implicit $exec + %21:sreg_64_xexec_xnull = REG_SEQUENCE killed %3.sub0, %subreg.sub0, %3.sub1, %subreg.sub1 + %22:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + GLOBAL_ATOMIC_ADD_F32_SADDR killed %22, killed %20, killed %21, 0, 0, implicit $exec bb.3: successors: %bb.4(0x80000000) - SI_END_CF killed %3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + SI_END_CF killed %17, implicit-def dead $exec, implicit-def dead $scc, implicit $exec bb.4: - SI_END_CF killed %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + SI_END_CF killed %13, implicit-def dead $exec, implicit-def dead $scc, implicit $exec S_ENDPGM 0 ... _______________________________________________ llvm-branch-commits mailing list [email protected] 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