llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: None (llvmbot) <details> <summary>Changes</summary> Backport 3bab75245a2bbbec36206f7e0c569c17a1a487e6 Requested by: @<!-- -->topperc --- Patch is 64.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/177101.diff 10 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td (+11-10) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td (+3-2) - (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-sdnode.ll (+20-20) - (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-sdnode.ll (+20-20) - (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-sdnode.ll (+20-20) - (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-sdnode.ll (+20-20) - (modified) llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll (+13-13) - (modified) llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll (+12-12) - (modified) llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll (+12-12) - (modified) llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll (+12-12) ``````````diff diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td index 1bdbfe40b1521..4a57b7f7f15b3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -1233,10 +1233,11 @@ foreach fvti = AllFloatAndBF16Vectors in { // NOTE: We choose VFMADD because it has the most commuting freedom. So it // works best with how TwoAddressInstructionPass tries commuting. defvar suffix = fvti.LMul.MX # "_E" # fvti.SEW; + defvar alt = !if(!eq(fvti.Scalar, bf16), "_ALT", ""); let Predicates = GetVTypePredicates<fvti>.Predicates in { def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd, fvti.RegClass:$rs2)), - (!cast<Instruction>("PseudoVFMADD_VV_"# suffix) + (!cast<Instruction>("PseudoVFMADD" # alt # "_VV_"# suffix) fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, // Value to indicate no rounding mode change in // RISCVInsertReadWriteCSR @@ -1244,7 +1245,7 @@ foreach fvti = AllFloatAndBF16Vectors in { fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))), - (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix) + (!cast<Instruction>("PseudoVFMSUB" # alt # "_VV_"# suffix) fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, // Value to indicate no rounding mode change in // RISCVInsertReadWriteCSR @@ -1252,7 +1253,7 @@ foreach fvti = AllFloatAndBF16Vectors in { fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))), - (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix) + (!cast<Instruction>("PseudoVFNMADD" # alt # "_VV_"# suffix) fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, // Value to indicate no rounding mode change in // RISCVInsertReadWriteCSR @@ -1260,7 +1261,7 @@ foreach fvti = AllFloatAndBF16Vectors in { fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd, fvti.RegClass:$rs2)), - (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix) + (!cast<Instruction>("PseudoVFNMSUB" # alt # "_VV_"# suffix) fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, // Value to indicate no rounding mode change in // RISCVInsertReadWriteCSR @@ -1271,7 +1272,7 @@ foreach fvti = AllFloatAndBF16Vectors in { // commutable. def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), fvti.RegClass:$rd, fvti.RegClass:$rs2)), - (!cast<Instruction>("PseudoVFMADD_V" # fvti.ScalarSuffix # "_" # suffix) + (!cast<Instruction>("PseudoVFMADD" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix) fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, // Value to indicate no rounding mode change in // RISCVInsertReadWriteCSR @@ -1279,7 +1280,7 @@ foreach fvti = AllFloatAndBF16Vectors in { fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))), - (!cast<Instruction>("PseudoVFMSUB_V" # fvti.ScalarSuffix # "_" # suffix) + (!cast<Instruction>("PseudoVFMSUB" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix) fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, // Value to indicate no rounding mode change in // RISCVInsertReadWriteCSR @@ -1288,7 +1289,7 @@ foreach fvti = AllFloatAndBF16Vectors in { def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), (fneg fvti.RegClass:$rd), (fneg fvti.RegClass:$rs2))), - (!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix) + (!cast<Instruction>("PseudoVFNMADD" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix) fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, // Value to indicate no rounding mode change in // RISCVInsertReadWriteCSR @@ -1296,7 +1297,7 @@ foreach fvti = AllFloatAndBF16Vectors in { fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), (fneg fvti.RegClass:$rd), fvti.RegClass:$rs2)), - (!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix) + (!cast<Instruction>("PseudoVFNMSUB" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix) fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, // Value to indicate no rounding mode change in // RISCVInsertReadWriteCSR @@ -1306,7 +1307,7 @@ foreach fvti = AllFloatAndBF16Vectors in { // The splat might be negated. def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)), fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))), - (!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix) + (!cast<Instruction>("PseudoVFNMADD" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix) fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, // Value to indicate no rounding mode change in // RISCVInsertReadWriteCSR @@ -1314,7 +1315,7 @@ foreach fvti = AllFloatAndBF16Vectors in { fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)), fvti.RegClass:$rd, fvti.RegClass:$rs2)), - (!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix) + (!cast<Instruction>("PseudoVFNMSUB" # alt # "_V" # fvti.ScalarSuffix # "_" # suffix) fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, // Value to indicate no rounding mode change in // RISCVInsertReadWriteCSR diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index ab94566350319..77a48cd1a0fc9 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -1814,11 +1814,12 @@ multiclass VPatFPMulAddVL_VV_VF<SDPatternOperator vop, string instruction_name> multiclass VPatFPMulAddVL_VV_VF_RM<SDPatternOperator vop, string instruction_name> { foreach vti = AllFloatAndBF16Vectors in { defvar suffix = vti.LMul.MX # "_E" # vti.SEW; + defvar alt = !if(!eq(vti.Scalar, bf16), "_ALT", ""); let Predicates = GetVTypePredicates<vti>.Predicates in { def : Pat<(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rd, vti.RegClass:$rs2, (vti.Mask VMV0:$vm), VLOpFrag)), - (!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK") + (!cast<Instruction>(instruction_name # alt # "_VV_"# suffix #"_MASK") vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, (vti.Mask VMV0:$vm), // Value to indicate no rounding mode change in @@ -1830,7 +1831,7 @@ multiclass VPatFPMulAddVL_VV_VF_RM<SDPatternOperator vop, string instruction_nam vti.RegClass:$rd, vti.RegClass:$rs2, (vti.Mask VMV0:$vm), VLOpFrag)), - (!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") + (!cast<Instruction>(instruction_name # alt # "_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, (vti.Mask VMV0:$vm), // Value to indicate no rounding mode change in diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-sdnode.ll index 814ee7739ee62..89cf847bb2c70 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-sdnode.ll @@ -7,7 +7,7 @@ define <1 x bfloat> @vfmadd_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x bfloat> %vc) { ; CHECK-LABEL: vfmadd_vv_v1bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret %vd = call <1 x bfloat> @llvm.fma.v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x bfloat> %vc) @@ -17,7 +17,7 @@ define <1 x bfloat> @vfmadd_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x b define <1 x bfloat> @vfmadd_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat %c) { ; CHECK-LABEL: vfmadd_vf_v1bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 ; CHECK-NEXT: ret %head = insertelement <1 x bfloat> poison, bfloat %c, i32 0 @@ -29,7 +29,7 @@ define <1 x bfloat> @vfmadd_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat define <2 x bfloat> @vfmadd_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x bfloat> %vc) { ; CHECK-LABEL: vfmadd_vv_v2bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; CHECK-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret %vd = call <2 x bfloat> @llvm.fma.v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x bfloat> %vc) @@ -39,7 +39,7 @@ define <2 x bfloat> @vfmadd_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x b define <2 x bfloat> @vfmadd_vf_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, bfloat %c) { ; CHECK-LABEL: vfmadd_vf_v2bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; CHECK-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 ; CHECK-NEXT: ret %head = insertelement <2 x bfloat> poison, bfloat %c, i32 0 @@ -51,7 +51,7 @@ define <2 x bfloat> @vfmadd_vf_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, bfloat define <4 x bfloat> @vfmadd_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x bfloat> %vc) { ; CHECK-LABEL: vfmadd_vv_v4bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; CHECK-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret %vd = call <4 x bfloat> @llvm.fma.v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x bfloat> %vc) @@ -61,7 +61,7 @@ define <4 x bfloat> @vfmadd_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x b define <4 x bfloat> @vfmadd_vf_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, bfloat %c) { ; CHECK-LABEL: vfmadd_vf_v4bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; CHECK-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 ; CHECK-NEXT: ret %head = insertelement <4 x bfloat> poison, bfloat %c, i32 0 @@ -73,7 +73,7 @@ define <4 x bfloat> @vfmadd_vf_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, bfloat define <8 x bfloat> @vfmadd_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x bfloat> %vc) { ; CHECK-LABEL: vfmadd_vv_v8bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret %vd = call <8 x bfloat> @llvm.fma.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x bfloat> %vc) @@ -83,7 +83,7 @@ define <8 x bfloat> @vfmadd_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x b define <8 x bfloat> @vfmadd_vf_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, bfloat %c) { ; CHECK-LABEL: vfmadd_vf_v8bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 ; CHECK-NEXT: ret %head = insertelement <8 x bfloat> poison, bfloat %c, i32 0 @@ -95,7 +95,7 @@ define <8 x bfloat> @vfmadd_vf_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, bfloat define <16 x bfloat> @vfmadd_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x bfloat> %vc) { ; CHECK-LABEL: vfmadd_vv_v16bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; CHECK-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: ret %vd = call <16 x bfloat> @llvm.fma.v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x bfloat> %vc) @@ -105,7 +105,7 @@ define <16 x bfloat> @vfmadd_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <1 define <16 x bfloat> @vfmadd_vf_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, bfloat %c) { ; CHECK-LABEL: vfmadd_vf_v16bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; CHECK-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma ; CHECK-NEXT: vfmadd.vf v8, fa0, v10 ; CHECK-NEXT: ret %head = insertelement <16 x bfloat> poison, bfloat %c, i32 0 @@ -117,7 +117,7 @@ define <16 x bfloat> @vfmadd_vf_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, bf define <1 x bfloat> @vfmacc_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x bfloat> %vc) { ; CHECK-LABEL: vfmacc_vv_v1bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma ; CHECK-NEXT: vfmacc.vv v8, v10, v9 ; CHECK-NEXT: ret %vd = call <1 x bfloat> @llvm.fma.v1bf16(<1 x bfloat> %vb, <1 x bfloat> %vc, <1 x bfloat> %va) @@ -127,7 +127,7 @@ define <1 x bfloat> @vfmacc_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x b define <1 x bfloat> @vfmacc_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat %c) { ; CHECK-LABEL: vfmacc_vf_v1bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 ; CHECK-NEXT: ret %head = insertelement <1 x bfloat> poison, bfloat %c, i32 0 @@ -139,7 +139,7 @@ define <1 x bfloat> @vfmacc_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat define <2 x bfloat> @vfmacc_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x bfloat> %vc) { ; CHECK-LABEL: vfmacc_vv_v2bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; CHECK-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma ; CHECK-NEXT: vfmacc.vv v8, v10, v9 ; CHECK-NEXT: ret %vd = call <2 x bfloat> @llvm.fma.v2bf16(<2 x bfloat> %vb, <2 x bfloat> %vc, <2 x bfloat> %va) @@ -149,7 +149,7 @@ define <2 x bfloat> @vfmacc_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x b define <2 x bfloat> @vfmacc_vf_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, bfloat %c) { ; CHECK-LABEL: vfmacc_vf_v2bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; CHECK-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 ; CHECK-NEXT: ret %head = insertelement <2 x bfloat> poison, bfloat %c, i32 0 @@ -161,7 +161,7 @@ define <2 x bfloat> @vfmacc_vf_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, bfloat define <4 x bfloat> @vfmacc_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x bfloat> %vc) { ; CHECK-LABEL: vfmacc_vv_v4bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; CHECK-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma ; CHECK-NEXT: vfmacc.vv v8, v10, v9 ; CHECK-NEXT: ret %vd = call <4 x bfloat> @llvm.fma.v4bf16(<4 x bfloat> %vb, <4 x bfloat> %vc, <4 x bfloat> %va) @@ -171,7 +171,7 @@ define <4 x bfloat> @vfmacc_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x b define <4 x bfloat> @vfmacc_vf_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, bfloat %c) { ; CHECK-LABEL: vfmacc_vf_v4bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; CHECK-NEXT: vsetivli zero, 4, e16alt, mf2, ta, ma ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 ; CHECK-NEXT: ret %head = insertelement <4 x bfloat> poison, bfloat %c, i32 0 @@ -183,7 +183,7 @@ define <4 x bfloat> @vfmacc_vf_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, bfloat define <8 x bfloat> @vfmacc_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x bfloat> %vc) { ; CHECK-LABEL: vfmacc_vv_v8bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma ; CHECK-NEXT: vfmacc.vv v8, v10, v9 ; CHECK-NEXT: ret %vd = call <8 x bfloat> @llvm.fma.v8bf16(<8 x bfloat> %vb, <8 x bfloat> %vc, <8 x bfloat> %va) @@ -193,7 +193,7 @@ define <8 x bfloat> @vfmacc_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x b define <8 x bfloat> @vfmacc_vf_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, bfloat %c) { ; CHECK-LABEL: vfmacc_vf_v8bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-NEXT: vsetivli zero, 8, e16alt, m1, ta, ma ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 ; CHECK-NEXT: ret %head = insertelement <8 x bfloat> poison, bfloat %c, i32 0 @@ -205,7 +205,7 @@ define <8 x bfloat> @vfmacc_vf_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, bfloat define <16 x bfloat> @vfmacc_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <16 x bfloat> %vc) { ; CHECK-LABEL: vfmacc_vv_v16bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; CHECK-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma ; CHECK-NEXT: vfmacc.vv v8, v12, v10 ; CHECK-NEXT: ret %vd = call <16 x bfloat> @llvm.fma.v16bf16(<16 x bfloat> %vb, <16 x bfloat> %vc, <16 x bfloat> %va) @@ -215,7 +215,7 @@ define <16 x bfloat> @vfmacc_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <1 define <16 x bfloat> @vfmacc_vf_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, bfloat %c) { ; CHECK-LABEL: vfmacc_vf_v16bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; CHECK-NEXT: vsetivli zero, 16, e16alt, m2, ta, ma ; CHECK-NEXT: vfmacc.vf v8, fa0, v10 ; CHECK-NEXT: ret %head = insertelement <16 x bfloat> poison, bfloat %c, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-sdnode.ll index d3f43c21f1638..c50c371d5e4ef 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-sdnode.ll @@ -7,7 +7,7 @@ define <1 x bfloat> @vfmsub_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x bfloat> %vc) { ; CHECK-LABEL: vfmsub_vv_v1bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret %neg = fneg <1 x bfloat> %vc @@ -18,7 +18,7 @@ define <1 x bfloat> @vfmsub_vv_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, <1 x b define <1 x bfloat> @vfmsub_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat %c) { ; CHECK-LABEL: vfmsub_vf_v1bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; CHECK-NEXT: vsetivli zero, 1, e16alt, mf4, ta, ma ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 ; CHECK-NEXT: ret %head = insertelement <1 x bfloat> poison, bfloat %c, i32 0 @@ -31,7 +31,7 @@ define <1 x bfloat> @vfmsub_vf_v1bf16(<1 x bfloat> %va, <1 x bfloat> %vb, bfloat define <2 x bfloat> @vfmsub_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x bfloat> %vc) { ; CHECK-LABEL: vfmsub_vv_v2bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 2, e16,... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/177101 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
