llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-loongarch Author: None (llvmbot) <details> <summary>Changes</summary> Backport f537408bc4fee1b7edc6b703e68792957f85f133 Requested by: @<!-- -->zhaoqi5 --- Full diff: https://github.com/llvm/llvm-project/pull/177104.diff 2 Files Affected: - (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (-43) - (modified) llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll (+26-12) ``````````diff diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index bc9ae3eafb3b2..accf887b292dc 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -481,11 +481,6 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM, setTargetDAGCombine(ISD::BITCAST); } - // Set DAG combine for 'LASX' feature. - - if (Subtarget.hasExtLASX()) - setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); - // Compute derived properties from the register classes. computeRegisterProperties(Subtarget.getRegisterInfo()); @@ -6854,42 +6849,6 @@ performSPLIT_PAIR_F64Combine(SDNode *N, SelectionDAG &DAG, return SDValue(); } -static SDValue -performEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, - TargetLowering::DAGCombinerInfo &DCI, - const LoongArchSubtarget &Subtarget) { - if (!DCI.isBeforeLegalize()) - return SDValue(); - - MVT EltVT = N->getSimpleValueType(0); - SDValue Vec = N->getOperand(0); - EVT VecTy = Vec->getValueType(0); - SDValue Idx = N->getOperand(1); - unsigned IdxOp = Idx.getOpcode(); - SDLoc DL(N); - - if (!VecTy.is256BitVector() || isa<ConstantSDNode>(Idx)) - return SDValue(); - - // Combine: - // t2 = truncate t1 - // t3 = {zero/sign/any}_extend t2 - // t4 = extract_vector_elt t0, t3 - // to: - // t4 = extract_vector_elt t0, t1 - if (IdxOp == ISD::ZERO_EXTEND || IdxOp == ISD::SIGN_EXTEND || - IdxOp == ISD::ANY_EXTEND) { - SDValue IdxOrig = Idx.getOperand(0); - if (!(IdxOrig.getOpcode() == ISD::TRUNCATE)) - return SDValue(); - - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vec, - IdxOrig.getOperand(0)); - } - - return SDValue(); -} - /// Do target-specific dag combines on LoongArchISD::VANDN nodes. static SDValue performVANDNCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, @@ -6986,8 +6945,6 @@ SDValue LoongArchTargetLowering::PerformDAGCombine(SDNode *N, return performVMSKLTZCombine(N, DAG, DCI, Subtarget); case LoongArchISD::SPLIT_PAIR_F64: return performSPLIT_PAIR_F64Combine(N, DAG, DCI, Subtarget); - case ISD::EXTRACT_VECTOR_ELT: - return performEXTRACT_VECTOR_ELTCombine(N, DAG, DCI, Subtarget); case LoongArchISD::VANDN: return performVANDNCombine(N, DAG, DCI, Subtarget); } diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll index 60b51755681a4..0f598f65dc647 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll @@ -104,7 +104,8 @@ define void @extract_32xi8_idx(ptr %src, ptr %dst, i32 %idx) nounwind { ; LA64: # %bb.0: ; LA64-NEXT: xvld $xr0, $a0, 0 ; LA64-NEXT: xvpermi.q $xr1, $xr0, 1 -; LA64-NEXT: movgr2fr.w $fa2, $a2 +; LA64-NEXT: bstrpick.d $a0, $a2, 31, 0 +; LA64-NEXT: movgr2fr.w $fa2, $a0 ; LA64-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2 ; LA64-NEXT: xvstelm.b $xr0, $a1, 0, 0 ; LA64-NEXT: ret @@ -128,7 +129,8 @@ define void @extract_16xi16_idx(ptr %src, ptr %dst, i32 %idx) nounwind { ; LA64: # %bb.0: ; LA64-NEXT: xvld $xr0, $a0, 0 ; LA64-NEXT: xvpermi.q $xr1, $xr0, 1 -; LA64-NEXT: movgr2fr.w $fa2, $a2 +; LA64-NEXT: bstrpick.d $a0, $a2, 31, 0 +; LA64-NEXT: movgr2fr.w $fa2, $a0 ; LA64-NEXT: xvshuf.h $xr2, $xr1, $xr0 ; LA64-NEXT: xvstelm.h $xr2, $a1, 0, 0 ; LA64-NEXT: ret @@ -151,7 +153,8 @@ define void @extract_8xi32_idx(ptr %src, ptr %dst, i32 %idx) nounwind { ; LA64-LABEL: extract_8xi32_idx: ; LA64: # %bb.0: ; LA64-NEXT: xvld $xr0, $a0, 0 -; LA64-NEXT: xvreplgr2vr.w $xr1, $a2 +; LA64-NEXT: bstrpick.d $a0, $a2, 31, 0 +; LA64-NEXT: xvreplgr2vr.w $xr1, $a0 ; LA64-NEXT: xvperm.w $xr0, $xr0, $xr1 ; LA64-NEXT: xvstelm.w $xr0, $a1, 0, 0 ; LA64-NEXT: ret @@ -181,7 +184,8 @@ define void @extract_4xi64_idx(ptr %src, ptr %dst, i32 %idx) nounwind { ; LA64: # %bb.0: ; LA64-NEXT: xvld $xr0, $a0, 0 ; LA64-NEXT: xvpermi.q $xr1, $xr0, 1 -; LA64-NEXT: movgr2fr.w $fa2, $a2 +; LA64-NEXT: bstrpick.d $a0, $a2, 31, 0 +; LA64-NEXT: movgr2fr.w $fa2, $a0 ; LA64-NEXT: xvshuf.d $xr2, $xr1, $xr0 ; LA64-NEXT: xvstelm.d $xr2, $a1, 0, 0 ; LA64-NEXT: ret @@ -192,13 +196,22 @@ define void @extract_4xi64_idx(ptr %src, ptr %dst, i32 %idx) nounwind { } define void @extract_8xfloat_idx(ptr %src, ptr %dst, i32 %idx) nounwind { -; CHECK-LABEL: extract_8xfloat_idx: -; CHECK: # %bb.0: -; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvreplgr2vr.w $xr1, $a2 -; CHECK-NEXT: xvperm.w $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: extract_8xfloat_idx: +; LA32: # %bb.0: +; LA32-NEXT: xvld $xr0, $a0, 0 +; LA32-NEXT: xvreplgr2vr.w $xr1, $a2 +; LA32-NEXT: xvperm.w $xr0, $xr0, $xr1 +; LA32-NEXT: xvstelm.w $xr0, $a1, 0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: extract_8xfloat_idx: +; LA64: # %bb.0: +; LA64-NEXT: xvld $xr0, $a0, 0 +; LA64-NEXT: bstrpick.d $a0, $a2, 31, 0 +; LA64-NEXT: xvreplgr2vr.w $xr1, $a0 +; LA64-NEXT: xvperm.w $xr0, $xr0, $xr1 +; LA64-NEXT: xvstelm.w $xr0, $a1, 0, 0 +; LA64-NEXT: ret %v = load volatile <8 x float>, ptr %src %e = extractelement <8 x float> %v, i32 %idx store float %e, ptr %dst @@ -219,7 +232,8 @@ define void @extract_4xdouble_idx(ptr %src, ptr %dst, i32 %idx) nounwind { ; LA64: # %bb.0: ; LA64-NEXT: xvld $xr0, $a0, 0 ; LA64-NEXT: xvpermi.q $xr1, $xr0, 1 -; LA64-NEXT: movgr2fr.w $fa2, $a2 +; LA64-NEXT: bstrpick.d $a0, $a2, 31, 0 +; LA64-NEXT: movgr2fr.w $fa2, $a0 ; LA64-NEXT: xvshuf.d $xr2, $xr1, $xr0 ; LA64-NEXT: xvstelm.d $xr2, $a1, 0, 0 ; LA64-NEXT: ret `````````` </details> https://github.com/llvm/llvm-project/pull/177104 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
