llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Mariusz Sikora (mariusz-sikora-at-amd) <details> <summary>Changes</summary> --- Patch is 139.63 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/177618.diff 4 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+1) - (modified) llvm/lib/Target/AMDGPU/SOPInstructions.td (+157-108) - (added) llvm/test/MC/AMDGPU/gfx13_asm_sop1.s (+3136) - (added) llvm/test/MC/AMDGPU/gfx13_asm_sop1_alias.s (+69) ``````````diff diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index 3ed93cd80fd92..32f8c50b6e955 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -2070,6 +2070,7 @@ def FeatureISAVersion13 : FeatureSet< FeatureCvtPkF16F32Inst, FeatureF16BF16ToFP6BF6ConversionScaleInsts, FeatureIEEEMinimumMaximumInsts, + FeatureSWakeupBarrier, FeatureClusters, FeatureCubeInsts, FeatureLerpInst, diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 030496e1ca8dd..b30b5ead0a4eb 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -2123,7 +2123,34 @@ class Select_gfx6_gfx7<string opName> : SIMCInstr<opName, SIEncodingFamily.SI> { } //===----------------------------------------------------------------------===// -// SOP1 - GFX11, GFX12 +// SOP1 - GFX13 +//===----------------------------------------------------------------------===// + +multiclass SOP1_Real_gfx13<bits<8> op, string name = !tolower(NAME)> { + defvar ps = !cast<SOP1_Pseudo>(NAME); + def _gfx13 : SOP1_Real<op, ps, name>, + Select<GFX13Gen, ps.Mnemonic>; + if !ne(ps.Mnemonic, name) then + def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX13Only]>; +} + +multiclass SOP1_M0_Real_gfx13<bits<8> op> { + defvar ps = !cast<SOP1_Pseudo>(NAME); + def _gfx13 : SOP1_Real<op, ps>, Select<GFX13Gen, ps.PseudoInstr> { + let Inst{7-0} = M0_gfx11plus.HWEncoding{7-0}; // Set Src0 encoding to M0 + } +} + +multiclass SOP1_IMM_Real_gfx13<bits<8> op> { + defvar ps = !cast<SOP1_Pseudo>(NAME); + def _gfx13 : SOP1_Real<op, ps>, + Select<GFX13Gen, ps.PseudoInstr>; +} + +defm S_GET_SHADER_CYCLES_U64 : SOP1_Real_gfx13<0x011>; + +//===----------------------------------------------------------------------===// +// SOP1 - GFX11, GFX12, GFX13 //===----------------------------------------------------------------------===// multiclass SOP1_Real_gfx11<bits<8> op, string name = !tolower(NAME)> { @@ -2142,23 +2169,29 @@ multiclass SOP1_Real_gfx12<bits<8> op, string name = !tolower(NAME)> { Select<GFX12Gen, ps.PseudoInstr>; if !ne(ps.Mnemonic, name) then def : AMDGPUMnemonicAlias<ps.Mnemonic, name> { - let AssemblerPredicate = isGFX12Plus; + let AssemblerPredicate = isGFX12Only; } } multiclass SOP1_M0_Real_gfx12<bits<8> op> { - def _gfx12 : SOP1_Real<op, !cast<SOP1_Pseudo>(NAME)>, - Select<GFX12Gen, !cast<SOP1_Pseudo>(NAME).PseudoInstr> { + defvar ps = !cast<SOP1_Pseudo>(NAME); + def _gfx12 : SOP1_Real<op, ps>, Select<GFX12Gen, ps.PseudoInstr> { let Inst{7-0} = M0_gfx11plus.HWEncoding{7-0}; // Set Src0 encoding to M0 } } +multiclass SOP1_M0_Real_gfx12_gfx13<bits<8> op> : + SOP1_M0_Real_gfx12<op>, SOP1_M0_Real_gfx13<op>; + multiclass SOP1_IMM_Real_gfx12<bits<8> op> { defvar ps = !cast<SOP1_Pseudo>(NAME); def _gfx12 : SOP1_Real<op, ps>, Select<GFX12Gen, ps.PseudoInstr>; } +multiclass SOP1_IMM_Real_gfx12_gfx13<bits<8> op> : + SOP1_IMM_Real_gfx12<op>, SOP1_IMM_Real_gfx13<op>; + multiclass SOP1_Real_gfx11_gfx12<bits<8> op, string name = !tolower(NAME)> : SOP1_Real_gfx11<op, name>, SOP1_Real_gfx12<op, name>; @@ -2171,6 +2204,12 @@ multiclass SOP1_Real_gfx1250<bits<8> op, string name = !tolower(NAME)> { def : AMDGPUMnemonicAlias<ps.Mnemonic, name>; } +multiclass SOP1_Real_gfx11_gfx12_gfx13<bits<8> op> : + SOP1_Real_gfx11<op>, SOP1_Real_gfx12<op>, SOP1_Real_gfx13<op>; + +multiclass SOP1_Real_gfx12_gfx13<bits<8> op> : + SOP1_Real_gfx12<op>, SOP1_Real_gfx13<op>; + defm S_MOV_B32 : SOP1_Real_gfx11_gfx12<0x000>; defm S_MOV_B64 : SOP1_Real_gfx11_gfx12<0x001>; defm S_CMOV_B32 : SOP1_Real_gfx11_gfx12<0x002>; @@ -2239,49 +2278,49 @@ defm S_GETPC_B64 : SOP1_Real_gfx1250<0x047, "s_get_pc_i64">; defm S_SETPC_B64 : SOP1_Real_gfx1250<0x048, "s_set_pc_i64">; defm S_SWAPPC_B64 : SOP1_Real_gfx1250<0x049, "s_swap_pc_i64">; defm S_RFE_B64 : SOP1_Real_gfx1250<0x04a, "s_rfe_i64">; -defm S_SENDMSG_RTN_B32 : SOP1_Real_gfx11_gfx12<0x04c>; -defm S_SENDMSG_RTN_B64 : SOP1_Real_gfx11_gfx12<0x04d>; -defm S_BARRIER_SIGNAL_M0 : SOP1_M0_Real_gfx12<0x04e>; -defm S_BARRIER_SIGNAL_ISFIRST_M0 : SOP1_M0_Real_gfx12<0x04f>; -defm S_GET_BARRIER_STATE_M0 : SOP1_M0_Real_gfx12<0x050>; -defm S_BARRIER_INIT_M0 : SOP1_M0_Real_gfx12<0x051>; -defm S_BARRIER_JOIN_M0 : SOP1_M0_Real_gfx12<0x052>; -defm S_BARRIER_SIGNAL_IMM : SOP1_IMM_Real_gfx12<0x04e>; -defm S_BARRIER_SIGNAL_ISFIRST_IMM : SOP1_IMM_Real_gfx12<0x04f>; -defm S_GET_BARRIER_STATE_IMM : SOP1_IMM_Real_gfx12<0x050>; -defm S_BARRIER_INIT_IMM : SOP1_IMM_Real_gfx12<0x051>; -defm S_BARRIER_JOIN_IMM : SOP1_IMM_Real_gfx12<0x052>; -defm S_ALLOC_VGPR : SOP1_Real_gfx12<0x053>; -defm S_SLEEP_VAR : SOP1_IMM_Real_gfx12<0x058>; - -// GFX1250 +defm S_SENDMSG_RTN_B32 : SOP1_Real_gfx11_gfx12_gfx13<0x04c>; +defm S_SENDMSG_RTN_B64 : SOP1_Real_gfx11_gfx12_gfx13<0x04d>; +defm S_BARRIER_SIGNAL_M0 : SOP1_M0_Real_gfx12_gfx13<0x04e>; +defm S_BARRIER_SIGNAL_ISFIRST_M0 : SOP1_M0_Real_gfx12_gfx13<0x04f>; +defm S_GET_BARRIER_STATE_M0 : SOP1_M0_Real_gfx12_gfx13<0x050>; +defm S_BARRIER_INIT_M0 : SOP1_M0_Real_gfx12_gfx13<0x051>; +defm S_BARRIER_JOIN_M0 : SOP1_M0_Real_gfx12_gfx13<0x052>; +defm S_BARRIER_SIGNAL_IMM : SOP1_IMM_Real_gfx12_gfx13<0x04e>; +defm S_BARRIER_SIGNAL_ISFIRST_IMM : SOP1_IMM_Real_gfx12_gfx13<0x04f>; +defm S_GET_BARRIER_STATE_IMM : SOP1_IMM_Real_gfx12_gfx13<0x050>; +defm S_BARRIER_INIT_IMM : SOP1_IMM_Real_gfx12_gfx13<0x051>; +defm S_BARRIER_JOIN_IMM : SOP1_IMM_Real_gfx12_gfx13<0x052>; +defm S_ALLOC_VGPR : SOP1_Real_gfx12_gfx13<0x053>; +defm S_SLEEP_VAR : SOP1_IMM_Real_gfx12_gfx13<0x058>; + +// GFX1250, GFX13 defm S_GET_SHADER_CYCLES_U64 : SOP1_Real_gfx12<0x06>; -defm S_ADD_PC_I64 : SOP1_Real_gfx12<0x04b>; -defm S_WAKEUP_BARRIER_M0 : SOP1_M0_Real_gfx12<0x057>; -defm S_WAKEUP_BARRIER_IMM : SOP1_IMM_Real_gfx12<0x057>; +defm S_ADD_PC_I64 : SOP1_Real_gfx12_gfx13<0x04b>; +defm S_WAKEUP_BARRIER_M0 : SOP1_M0_Real_gfx12_gfx13<0x057>; +defm S_WAKEUP_BARRIER_IMM : SOP1_IMM_Real_gfx12_gfx13<0x057>; //===----------------------------------------------------------------------===// -// SOP1 - GFX1150, GFX12 +// SOP1 - GFX1150, GFX12, GFX13 //===----------------------------------------------------------------------===// -defm S_CEIL_F32 : SOP1_Real_gfx11_gfx12<0x060>; -defm S_FLOOR_F32 : SOP1_Real_gfx11_gfx12<0x061>; -defm S_TRUNC_F32 : SOP1_Real_gfx11_gfx12<0x062>; -defm S_RNDNE_F32 : SOP1_Real_gfx11_gfx12<0x063>; -defm S_CVT_F32_I32 : SOP1_Real_gfx11_gfx12<0x064>; -defm S_CVT_F32_U32 : SOP1_Real_gfx11_gfx12<0x065>; -defm S_CVT_I32_F32 : SOP1_Real_gfx11_gfx12<0x066>; -defm S_CVT_U32_F32 : SOP1_Real_gfx11_gfx12<0x067>; -defm S_CVT_F16_F32 : SOP1_Real_gfx11_gfx12<0x068>; -defm S_CVT_F32_F16 : SOP1_Real_gfx11_gfx12<0x069>; -defm S_CVT_HI_F32_F16 : SOP1_Real_gfx11_gfx12<0x06a>; -defm S_CEIL_F16 : SOP1_Real_gfx11_gfx12<0x06b>; -defm S_FLOOR_F16 : SOP1_Real_gfx11_gfx12<0x06c>; -defm S_TRUNC_F16 : SOP1_Real_gfx11_gfx12<0x06d>; -defm S_RNDNE_F16 : SOP1_Real_gfx11_gfx12<0x06e>; +defm S_CEIL_F32 : SOP1_Real_gfx11_gfx12_gfx13<0x060>; +defm S_FLOOR_F32 : SOP1_Real_gfx11_gfx12_gfx13<0x061>; +defm S_TRUNC_F32 : SOP1_Real_gfx11_gfx12_gfx13<0x062>; +defm S_RNDNE_F32 : SOP1_Real_gfx11_gfx12_gfx13<0x063>; +defm S_CVT_F32_I32 : SOP1_Real_gfx11_gfx12_gfx13<0x064>; +defm S_CVT_F32_U32 : SOP1_Real_gfx11_gfx12_gfx13<0x065>; +defm S_CVT_I32_F32 : SOP1_Real_gfx11_gfx12_gfx13<0x066>; +defm S_CVT_U32_F32 : SOP1_Real_gfx11_gfx12_gfx13<0x067>; +defm S_CVT_F16_F32 : SOP1_Real_gfx11_gfx12_gfx13<0x068>; +defm S_CVT_F32_F16 : SOP1_Real_gfx11_gfx12_gfx13<0x069>; +defm S_CVT_HI_F32_F16 : SOP1_Real_gfx11_gfx12_gfx13<0x06a>; +defm S_CEIL_F16 : SOP1_Real_gfx11_gfx12_gfx13<0x06b>; +defm S_FLOOR_F16 : SOP1_Real_gfx11_gfx12_gfx13<0x06c>; +defm S_TRUNC_F16 : SOP1_Real_gfx11_gfx12_gfx13<0x06d>; +defm S_RNDNE_F16 : SOP1_Real_gfx11_gfx12_gfx13<0x06e>; //===----------------------------------------------------------------------===// -// SOP1 - GFX10. +// SOP1 - GFX10, GFX13 //===----------------------------------------------------------------------===// multiclass SOP1_Real_gfx10<bits<8> op> { @@ -2290,30 +2329,33 @@ multiclass SOP1_Real_gfx10<bits<8> op> { Select<GFX10Gen, ps.PseudoInstr>; } -multiclass SOP1_Real_gfx10_gfx11_gfx12<bits<8> op> : - SOP1_Real_gfx10<op>, SOP1_Real_gfx11_gfx12<op>; +multiclass SOP1_Real_gfx10_gfx13<bits<8> op> : + SOP1_Real_gfx10<op>, SOP1_Real_gfx13<op>; -defm S_ANDN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x037>; -defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x038>; -defm S_ANDN1_WREXEC_B64 : SOP1_Real_gfx10<0x039>; -defm S_ANDN2_WREXEC_B64 : SOP1_Real_gfx10<0x03a>; -defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx10<0x03b>; -defm S_AND_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03c>; -defm S_OR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03d>; -defm S_XOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03e>; -defm S_ANDN2_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03f>; -defm S_ORN2_SAVEEXEC_B32 : SOP1_Real_gfx10<0x040>; -defm S_NAND_SAVEEXEC_B32 : SOP1_Real_gfx10<0x041>; -defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x042>; -defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x043>; -defm S_ANDN1_SAVEEXEC_B32 : SOP1_Real_gfx10<0x044>; -defm S_ORN1_SAVEEXEC_B32 : SOP1_Real_gfx10<0x045>; -defm S_ANDN1_WREXEC_B32 : SOP1_Real_gfx10<0x046>; -defm S_ANDN2_WREXEC_B32 : SOP1_Real_gfx10<0x047>; -defm S_MOVRELSD_2_B32 : SOP1_Real_gfx10<0x049>; +multiclass SOP1_Real_gfx10_Renamed_gfx13<bits<8> op, string gfx13_name> : + SOP1_Real_gfx10<op>, SOP1_Real_gfx13<op, gfx13_name>; + +defm S_ANDN1_SAVEEXEC_B64 : SOP1_Real_gfx10_Renamed_gfx13<0x37, "s_and_not0_saveexec_b64">; +defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_gfx10_Renamed_gfx13<0x38, "s_or_not0_saveexec_b64">; +defm S_ANDN1_WREXEC_B64 : SOP1_Real_gfx10_Renamed_gfx13<0x39, "s_and_not0_wrexec_b64">; +defm S_ANDN2_WREXEC_B64 : SOP1_Real_gfx10_Renamed_gfx13<0x3a, "s_and_not1_wrexec_b64">; +defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx10_gfx13<0x03b>; +defm S_AND_SAVEEXEC_B32 : SOP1_Real_gfx10_gfx13<0x03c>; +defm S_OR_SAVEEXEC_B32 : SOP1_Real_gfx10_gfx13<0x03d>; +defm S_XOR_SAVEEXEC_B32 : SOP1_Real_gfx10_gfx13<0x03e>; +defm S_ANDN2_SAVEEXEC_B32 : SOP1_Real_gfx10_Renamed_gfx13<0x3f, "s_and_not1_saveexec_b32">; +defm S_ORN2_SAVEEXEC_B32 : SOP1_Real_gfx10_Renamed_gfx13<0x40, "s_or_not1_saveexec_b32">; +defm S_NAND_SAVEEXEC_B32 : SOP1_Real_gfx10_gfx13<0x041>; +defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx10_gfx13<0x042>; +defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx10_gfx13<0x043>; +defm S_ANDN1_SAVEEXEC_B32 : SOP1_Real_gfx10_Renamed_gfx13<0x44, "s_and_not0_saveexec_b32">; +defm S_ORN1_SAVEEXEC_B32 : SOP1_Real_gfx10_Renamed_gfx13<0x45, "s_or_not0_saveexec_b32">; +defm S_ANDN1_WREXEC_B32 : SOP1_Real_gfx10_Renamed_gfx13<0x46, "s_and_not0_wrexec_b32">; +defm S_ANDN2_WREXEC_B32 : SOP1_Real_gfx10_Renamed_gfx13<0x47, "s_and_not1_wrexec_b32">; +defm S_MOVRELSD_2_B32 : SOP1_Real_gfx10_gfx13<0x049>; //===----------------------------------------------------------------------===// -// SOP1 - GFX6, GFX7, GFX10, GFX11. +// SOP1 - GFX6, GFX7, GFX10, GFX11, GFX13 //===----------------------------------------------------------------------===// @@ -2326,58 +2368,65 @@ multiclass SOP1_Real_gfx6_gfx7<bits<8> op> { multiclass SOP1_Real_gfx6_gfx7_gfx10<bits<8> op> : SOP1_Real_gfx6_gfx7<op>, SOP1_Real_gfx10<op>; -multiclass SOP1_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op> : - SOP1_Real_gfx6_gfx7<op>, SOP1_Real_gfx10_gfx11_gfx12<op>; +multiclass SOP1_Real_gfx6_gfx7_gfx10_gfx13<bits<8> op> : + SOP1_Real_gfx6_gfx7<op>, SOP1_Real_gfx10<op>, SOP1_Real_gfx13<op>; + +multiclass SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<bits<8> op, string gfx13_name> : + SOP1_Real_gfx6_gfx7<op>, SOP1_Real_gfx10<op>, SOP1_Real_gfx13<op, gfx13_name>; + +multiclass SOP1_Real_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13<bits<8> op> : + SOP1_Real_gfx6_gfx7<op>, SOP1_Real_gfx10<op>, SOP1_Real_gfx11<op>, + SOP1_Real_gfx12<op>, SOP1_Real_gfx13<op>; defm S_CBRANCH_JOIN : SOP1_Real_gfx6_gfx7<0x032>; -defm S_MOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x003>; -defm S_MOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x004>; -defm S_CMOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x005>; -defm S_CMOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x006>; -defm S_NOT_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x007>; -defm S_NOT_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x008>; -defm S_WQM_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x009>; -defm S_WQM_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00a>; -defm S_BREV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00b>; -defm S_BREV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00c>; -defm S_BCNT0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00d>; -defm S_BCNT0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00e>; -defm S_BCNT1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00f>; -defm S_BCNT1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x010>; +defm S_MOV_B32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x003>; +defm S_MOV_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x004>; +defm S_CMOV_B32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x005>; +defm S_CMOV_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x006>; +defm S_NOT_B32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x007>; +defm S_NOT_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x008>; +defm S_WQM_B32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x009>; +defm S_WQM_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x00a>; +defm S_BREV_B32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x00b>; +defm S_BREV_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x00c>; +defm S_BCNT0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x00d>; +defm S_BCNT0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x00e>; +defm S_BCNT1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x00f>; +defm S_BCNT1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x010>; defm S_FF0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x011>; defm S_FF0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x012>; -defm S_FF1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x013>; -defm S_FF1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x014>; -defm S_FLBIT_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x015>; -defm S_FLBIT_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x016>; -defm S_FLBIT_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x017>; -defm S_FLBIT_I32_I64 : SOP1_Real_gfx6_gfx7_gfx10<0x018>; -defm S_SEXT_I32_I8 : SOP1_Real_gfx6_gfx7_gfx10<0x019>; -defm S_SEXT_I32_I16 : SOP1_Real_gfx6_gfx7_gfx10<0x01a>; -defm S_BITSET0_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x01b>; -defm S_BITSET0_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01c>; -defm S_BITSET1_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x01d>; -defm S_BITSET1_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01e>; -defm S_GETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01f>; -defm S_SETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x020>; -defm S_SWAPPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x021>; -defm S_RFE_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x022>; -defm S_AND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x024>; -defm S_OR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x025>; -defm S_XOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x026>; -defm S_ANDN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x027>; -defm S_ORN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x028>; -defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x029>; -defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02a>; -defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02b>; -defm S_QUADMASK_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02c>; -defm S_QUADMASK_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02d>; -defm S_MOVRELS_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02e>; -defm S_MOVRELS_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02f>; -defm S_MOVRELD_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x030>; -defm S_MOVRELD_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x031>; -defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>; +defm S_FF1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<0x013, "s_ctz_i32_b32">; +defm S_FF1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<0x014, "s_ctz_i32_b64">; +defm S_FLBIT_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<0x015, "s_clz_i32_u32">; +defm S_FLBIT_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<0x016, "s_clz_i32_u64">; +defm S_FLBIT_I32 : SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<0x017, "s_cls_i32">; +defm S_FLBIT_I32_I64 : SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<0x018, "s_cls_i32_i64">; +defm S_SEXT_I32_I8 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x019>; +defm S_SEXT_I32_I16 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x01a>; +defm S_BITSET0_B32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x01b>; +defm S_BITSET0_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x01c>; +defm S_BITSET1_B32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x01d>; +defm S_BITSET1_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x01e>; +defm S_GETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<0x01f, "s_get_pc_i64">; +defm S_SETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<0x020, "s_set_pc_i64">; +defm S_SWAPPC_B64 : SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<0x021, "s_swap_pc_i64">; +defm S_RFE_B64 : SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<0x022, "s_rfe_i64">; +defm S_AND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x024>; +defm S_OR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x025>; +defm S_XOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x026>; +defm S_ANDN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<0x027, "s_and_not1_saveexec_b64">; +defm S_ORN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_Renamed_gfx13<0x028, "s_or_not1_saveexec_b64">; +defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x029>; +defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x02a>; +defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13<0x02b>; +defm S_QUADMASK_B32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x02c>; +defm S_QUADMASK_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x02d>; +defm S_MOVRELS_B32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x02e>; +defm S_MOVRELS_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x02f>; +defm S_MOVRELD_B32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x030>; +defm S_MOVRELD_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x031>; +defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10_gfx13<0x034>; //===----------------------------------------------------------------------===// // SOP2 - GFX12 diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx13_asm_sop1.s new file mode 100644 index 0000000000000..fcc2a32b1c606 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx13_asm_sop1.s @@ -0,0 +1,3136 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding < %s | FileCheck -check-prefixes=GFX13,GFX13-ASM %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1310 -disassemble -show-encoding | FileCheck --strict-whitespace --check-prefixes=GFX13,GFX13-DIS %s + +// INSTS= +// s_mov_b32 <OPS32> +// s_mov_b64 <OPS64> +// s_cmov_b32 <OPS32> +// s_cmov_b64 <OPS64> +// s_not_b32 <OPS32> +// s_not_b64 <OPS64> +// s_wqm_b32 <OPS32> +// s_wqm_b64 <OPS64> +// s_brev_b32 <OPS32> +// s_brev_b64 <OPS64> +// s_bcnt0_i32_b32 <OPS32> +// s_bcnt0_i32_b64 <OPS-32-64> +// s_bcnt1_i32_b32 <OPS32> +// s_bcnt1_i32_b64 <OPS-32-64> +// s_get_shader_cycl... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/177618 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
