llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> f16 is never legal for R600 so this should not be in the common base class. --- Full diff: https://github.com/llvm/llvm-project/pull/177629.diff 2 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (+2-11) - (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+3) ``````````diff diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 835d3ac1090d5..7652351e2e247 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -427,22 +427,13 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, Expand); setOperationAction(ISD::FREM, {MVT::f16, MVT::f32, MVT::f64}, Expand); - - if (Subtarget->has16BitInsts()) { - setOperationAction(ISD::IS_FPCLASS, {MVT::f16, MVT::f32, MVT::f64}, Legal); - setOperationAction({ISD::FLOG2, ISD::FEXP2}, MVT::f16, Legal); - } else { - setOperationAction(ISD::IS_FPCLASS, {MVT::f32, MVT::f64}, Legal); - setOperationAction({ISD::FLOG2, ISD::FEXP2}, MVT::f16, Custom); - } + setOperationAction(ISD::IS_FPCLASS, {MVT::f32, MVT::f64}, Legal); + setOperationAction({ISD::FLOG2, ISD::FEXP2}, MVT::f16, Custom); setOperationAction({ISD::FLOG10, ISD::FLOG, ISD::FEXP, ISD::FEXP10}, MVT::f16, Custom); setOperationAction(ISD::FCANONICALIZE, {MVT::f32, MVT::f64}, Legal); - if (Subtarget->has16BitInsts()) { - setOperationAction(ISD::FCANONICALIZE, MVT::f16, Legal); - } // FIXME: These IS_FPCLASS vector fp types are marked custom so it reaches // scalarization code. Can be removed when IS_FPCLASS expand isn't called by diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 657eec1d93076..6cf069de25898 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -504,6 +504,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, if (Subtarget->has16BitInsts()) { setOperationAction({ISD::FPOW, ISD::FPOWI}, MVT::f16, Promote); setOperationAction({ISD::FLOG, ISD::FEXP, ISD::FLOG10}, MVT::f16, Custom); + setOperationAction(ISD::IS_FPCLASS, {MVT::f16, MVT::f32, MVT::f64}, Legal); + setOperationAction({ISD::FLOG2, ISD::FEXP2}, MVT::f16, Legal); + setOperationAction(ISD::FCANONICALIZE, MVT::f16, Legal); } else { setOperationAction(ISD::FSQRT, MVT::f16, Custom); } `````````` </details> https://github.com/llvm/llvm-project/pull/177629 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
