Author: Sudharsan Veeravalli Date: 2026-01-28T09:29:46Z New Revision: 848164c632183b06c665fbba9e61e42bb4ac9635
URL: https://github.com/llvm/llvm-project/commit/848164c632183b06c665fbba9e61e42bb4ac9635 DIFF: https://github.com/llvm/llvm-project/commit/848164c632183b06c665fbba9e61e42bb4ac9635.diff LOG: [RISCV] Run combineOrToBitfieldInsert after DAG legalize (#177830) Not combing `OR` into `QC.INSB(I)` before DAG legalization helps known bits analysis to simplify the code if possible. (cherry picked from commit 3ed48305ab19bf0090d2ca714a37dd7b0667b6c2) Added: Modified: llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/test/CodeGen/RISCV/xqcibm-insert.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 2e9e5bbc65983..846e181b7e5af 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -17006,8 +17006,6 @@ static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const RISCVSubtarget &Subtarget) { SelectionDAG &DAG = DCI.DAG; - if (SDValue V = combineOrToBitfieldInsert(N, DAG, Subtarget)) - return V; if (SDValue V = combineOrAndToBitfieldInsert(N, DAG, Subtarget)) return V; if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget)) @@ -17015,9 +17013,12 @@ static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget)) return V; - if (DCI.isAfterLegalizeDAG()) + if (DCI.isAfterLegalizeDAG()) { + if (SDValue V = combineOrToBitfieldInsert(N, DAG, Subtarget)) + return V; if (SDValue V = combineDeMorganOfBoolean(N, DAG)) return V; + } // Look for Or of CZERO_EQZ/NEZ with same condition which is the select idiom. // We may be able to pull a common operation out of the true and false value. diff --git a/llvm/test/CodeGen/RISCV/xqcibm-insert.ll b/llvm/test/CodeGen/RISCV/xqcibm-insert.ll index 234bd233ec9af..043a184d34ccd 100644 --- a/llvm/test/CodeGen/RISCV/xqcibm-insert.ll +++ b/llvm/test/CodeGen/RISCV/xqcibm-insert.ll @@ -401,3 +401,25 @@ define i32 @bseti_i32_10(i32 %a) nounwind { %or = or i32 %a, 1024 ret i32 %or } + +define i1 @no_insbi_known_bits(i32 %arg) { +; RV32I-LABEL: no_insbi_known_bits: +; RV32I: # %bb.0: +; RV32I-NEXT: li a0, 1 +; RV32I-NEXT: ret +; +; RV32IXQCIBM-LABEL: no_insbi_known_bits: +; RV32IXQCIBM: # %bb.0: +; RV32IXQCIBM-NEXT: li a0, 1 +; RV32IXQCIBM-NEXT: ret +; +; RV32IXQCIBMZBS-LABEL: no_insbi_known_bits: +; RV32IXQCIBMZBS: # %bb.0: +; RV32IXQCIBMZBS-NEXT: li a0, 1 +; RV32IXQCIBMZBS-NEXT: ret + %a = or i32 %arg, 2147483647 + %b = call i32 @llvm.bswap.i32(i32 %a) + %and = and i32 %b, 127 + %res = icmp eq i32 %and, 127 + ret i1 %res +} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
