llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-x86 Author: None (llvmbot) <details> <summary>Changes</summary> Backport 618d71dc98df760d0c724cff6fa69b780e8c0372 49d2323447aec77c3d1ae8c941f3f8a126ff1480 Requested by: @<!-- -->RKSimon --- Full diff: https://github.com/llvm/llvm-project/pull/179117.diff 2 Files Affected: - (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+6-4) - (modified) llvm/test/CodeGen/X86/avx512-intrinsics.ll (+38) ``````````diff diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a354704c5958b..5935f2eb344e1 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -26574,7 +26574,8 @@ static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask, static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask, SDValue PreservedSrc, const X86Subtarget &Subtarget, - SelectionDAG &DAG) { + SelectionDAG &DAG, + unsigned UpperEltOpSrc = 0) { auto *MaskConst = dyn_cast<ConstantSDNode>(Mask); if (MaskConst && (MaskConst->getZExtValue() & 0x1)) return Op; @@ -26600,8 +26601,8 @@ static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask, SmallVector<int, 16> ShuffleMask(VT.getVectorNumElements()); std::iota(ShuffleMask.begin(), ShuffleMask.end(), 0); ShuffleMask[0] = VT.getVectorNumElements(); - return DAG.getVectorShuffle(VT, dl, Op.getOperand(0), PreservedSrc, - ShuffleMask); + return DAG.getVectorShuffle(VT, dl, Op.getOperand(UpperEltOpSrc), + PreservedSrc, ShuffleMask); } return DAG.getNode(X86ISD::SELECTS, dl, VT, IMask, Op, PreservedSrc); @@ -27262,7 +27263,8 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, if (Opc == X86ISD::VFIXUPIMM || Opc == X86ISD::VFIXUPIMM_SAE) return getVectorMaskingNode(FixupImm, Mask, Passthru, Subtarget, DAG); - return getScalarMaskingNode(FixupImm, Mask, Passthru, Subtarget, DAG); + return getScalarMaskingNode(FixupImm, Mask, Passthru, Subtarget, DAG, + /*UpperEltOpSrc=*/1); } case ROUNDP: { assert(IntrData->Opc0 == X86ISD::VRNDSCALE && "Unexpected opcode"); diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics.ll b/llvm/test/CodeGen/X86/avx512-intrinsics.ll index f9b5994a18d36..b979f7531cd36 100644 --- a/llvm/test/CodeGen/X86/avx512-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512-intrinsics.ll @@ -5518,6 +5518,15 @@ define <4 x float>@test_int_x86_avx512_mask_fixupimm_ss(<4 x float> %x0, <4 x fl ret <4 x float> %res4 } +define <4 x float>@test_int_x86_avx512_mask_fixupimm_ss_passthrough_zero_mask(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2) { +; CHECK-LABEL: test_int_x86_avx512_mask_fixupimm_ss_passthrough_zero_mask: +; CHECK: # %bb.0: +; CHECK-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; CHECK-NEXT: ret{{[l|q]}} + %res = call <4 x float> @llvm.x86.avx512.mask.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 -2, i32 4) + ret <4 x float> %res +} + declare <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float>, <4 x float>, <4 x i32>, i32, i8, i32) define <4 x float>@test_int_x86_avx512_maskz_fixupimm_ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i8 %x4) { @@ -5555,6 +5564,16 @@ define <4 x float>@test_int_x86_avx512_maskz_fixupimm_ss(<4 x float> %x0, <4 x f ret <4 x float> %res4 } +define <4 x float>@test_int_x86_avx512_maskz_fixupimm_ss_passthrough_zero_mask(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2) { +; CHECK-LABEL: test_int_x86_avx512_maskz_fixupimm_ss_passthrough_zero_mask: +; CHECK: # %bb.0: +; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; CHECK-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; CHECK-NEXT: ret{{[l|q]}} + %res = call <4 x float> @llvm.x86.avx512.maskz.fixupimm.ss(<4 x float> %x0, <4 x float> %x1, <4 x i32> %x2, i32 5, i8 -2, i32 4) + ret <4 x float> %res +} + declare <16 x float> @llvm.x86.avx512.mask.fixupimm.ps.512(<16 x float>, <16 x float>, <16 x i32>, i32, i16, i32) define <16 x float>@test_int_x86_avx512_mask_fixupimm_ps_512(<16 x float> %x0, <16 x float> %x1, <16 x i32> %x2, i16 %x4) { @@ -5680,6 +5699,15 @@ define <2 x double>@test_int_x86_avx512_mask_fixupimm_sd(<2 x double> %x0, <2 x ret <2 x double> %res4 } +define <2 x double>@test_int_x86_avx512_mask_fixupimm_sd_passthrough_zero_mask(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2) { +; CHECK-LABEL: test_int_x86_avx512_mask_fixupimm_sd_passthrough_zero_mask: +; CHECK: # %bb.0: +; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1] +; CHECK-NEXT: ret{{[l|q]}} + %res = call <2 x double> @llvm.x86.avx512.mask.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 5, i8 -2, i32 4) + ret <2 x double> %res +} + declare <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double>, <2 x double>, <2 x i64>, i32, i8, i32) define <2 x double>@test_int_x86_avx512_maskz_fixupimm_sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i8 %x4) { @@ -5717,6 +5745,16 @@ define <2 x double>@test_int_x86_avx512_maskz_fixupimm_sd(<2 x double> %x0, <2 x ret <2 x double> %res4 } +define <2 x double>@test_int_x86_avx512_maskz_fixupimm_sd_passthrough_zero_mask(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2) { +; CHECK-LABEL: test_int_x86_avx512_maskz_fixupimm_sd_passthrough_zero_mask: +; CHECK: # %bb.0: +; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1] +; CHECK-NEXT: ret{{[l|q]}} + %res = call <2 x double> @llvm.x86.avx512.maskz.fixupimm.sd(<2 x double> %x0, <2 x double> %x1, <2 x i64> %x2, i32 5, i8 -2, i32 4) + ret <2 x double> %res +} + declare double @llvm.fma.f64(double, double, double) #1 declare double @llvm.x86.avx512.vfmadd.f64(double, double, double, i32) #0 `````````` </details> https://github.com/llvm/llvm-project/pull/179117 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
