https://github.com/c-rhodes updated https://github.com/llvm/llvm-project/pull/178961
>From 38b58a2ea1bca1a2b6f1b13fc055ebce860b0da0 Mon Sep 17 00:00:00 2001 From: Jonas Paulsson <[email protected]> Date: Fri, 30 Jan 2026 14:55:07 -0600 Subject: [PATCH] [SystemZ] Bugfix: Add VLR16 to SystemZInstrInfo::copyPhysReg(). (#178932) Support COPYs involving higher FP16 regs (like F24H) with a new pseudo instruction 'VLR16'. This is needed with -O0/regalloc=fast, and probably in more cases as well. Fixes #178788. (cherry picked from commit 09f9a2892a412a73d42942e78eed9cde61c7a9e7) --- llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp | 1 + llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 2 ++ llvm/lib/Target/SystemZ/SystemZInstrVector.td | 1 + llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ14.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ15.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ16.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ17.td | 2 +- .../test/CodeGen/SystemZ/copy-physreg-vr16.ll | 35 +++++++++++++++++++ 9 files changed, 44 insertions(+), 5 deletions(-) create mode 100644 llvm/test/CodeGen/SystemZ/copy-physreg-vr16.ll diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp index 33e48f8ff1511..fcde175b42643 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -541,6 +541,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) { .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())); break; + case SystemZ::VLR16: case SystemZ::VLR32: case SystemZ::VLR64: LoweredMI = MCInstBuilder(SystemZ::VLR) diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index 43d0446fda2f2..913c62f9f8449 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -999,6 +999,8 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB, Opcode = SystemZ::LDR; else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg)) Opcode = SystemZ::LXR; + else if (SystemZ::VR16BitRegClass.contains(DestReg, SrcReg)) + Opcode = SystemZ::VLR16; else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg)) Opcode = SystemZ::VLR32; else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg)) diff --git a/llvm/lib/Target/SystemZ/SystemZInstrVector.td b/llvm/lib/Target/SystemZ/SystemZInstrVector.td index eb5753cfcde99..b0257be2eab89 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrVector.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrVector.td @@ -14,6 +14,7 @@ let Predicates = [FeatureVector] in { // Register move. let isMoveReg = 1 in { def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>; + def VLR16 : UnaryAliasVRR<null_frag, v16hb, v16hb>; def VLR32 : UnaryAliasVRR<null_frag, v32sb, v32sb>; def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>; } diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index 84c6ca21d7e93..afe8dec402548 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -1169,7 +1169,7 @@ def : InstRW<[WLat15, LSU, VecDF2, GroupAlone], (instregex "TD(C|G)XT$")>; // Vector: Move instructions //===----------------------------------------------------------------------===// -def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLR(32|64)?$")>; +def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLR(16|32|64)?$")>; def : InstRW<[WLat4, FXb, NormalGr], (instregex "VLGV(B|F|G|H)?$")>; def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLVG(B|F|G|H)?$")>; def : InstRW<[WLat3, FXb, NormalGr], (instregex "VLVGP(32)?$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td index b48ed08c8a189..dbbbcbee1c146 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td @@ -1187,7 +1187,7 @@ def : InstRW<[WLat15, LSU, VecDF2, GroupAlone], (instregex "TD(C|G)XT$")>; // Vector: Move instructions //===----------------------------------------------------------------------===// -def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLR(32|64)?$")>; +def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLR(16|32|64)?$")>; def : InstRW<[WLat3, FXb, NormalGr], (instregex "VLGV(B|F|G|H)?$")>; def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLVG(B|F|G|H)?$")>; def : InstRW<[WLat3, FXb, NormalGr], (instregex "VLVGP(32)?$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td index e3ec7a6994221..618e6dfa823d6 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td @@ -1209,7 +1209,7 @@ def : InstRW<[WLat15, LSU, VecDF2, GroupAlone], (instregex "TD(C|G)XT$")>; // Vector: Move instructions //===----------------------------------------------------------------------===// -def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLR(32|64)?$")>; +def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLR(16|32|64)?$")>; def : InstRW<[WLat3, FXb, NormalGr], (instregex "VLGV(B|F|G|H)?$")>; def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLVG(B|F|G|H)?$")>; def : InstRW<[WLat3, FXb, NormalGr], (instregex "VLVGP(32)?$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td index 4f904daec5052..0752b1c990091 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td @@ -1215,7 +1215,7 @@ def : InstRW<[WLat15, LSU, VecDF2, GroupAlone], (instregex "TD(C|G)XT$")>; // Vector: Move instructions //===----------------------------------------------------------------------===// -def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLR(32|64)?$")>; +def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLR(16|32|64)?$")>; def : InstRW<[WLat3, FXb, NormalGr], (instregex "VLGV(B|F|G|H)?$")>; def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLVG(B|F|G|H)?$")>; def : InstRW<[WLat3, FXb, NormalGr], (instregex "VLVGP(32)?$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ17.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ17.td index 3b5ce6c9b5a0e..f8677d1191ccf 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ17.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ17.td @@ -1230,7 +1230,7 @@ def : InstRW<[WLat15, LSU, VecDF2, GroupAlone], (instregex "TD(C|G)XT$")>; // Vector: Move instructions //===----------------------------------------------------------------------===// -def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLR(32|64)?$")>; +def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLR(16|32|64)?$")>; def : InstRW<[WLat3, FXb, NormalGr], (instregex "VLGV(B|F|G|H)?$")>; def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLVG(B|F|G|H)?$")>; def : InstRW<[WLat3, FXb, NormalGr], (instregex "VLVGP(32)?$")>; diff --git a/llvm/test/CodeGen/SystemZ/copy-physreg-vr16.ll b/llvm/test/CodeGen/SystemZ/copy-physreg-vr16.ll new file mode 100644 index 0000000000000..89fb8e4e8f820 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/copy-physreg-vr16.ll @@ -0,0 +1,35 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 -regalloc=fast -verify-machineinstrs \ +; RUN: | FileCheck %s + +; Test COPY to $f0 from $f24. +define half @fun0(<4 x half> %0) { +; CHECK-LABEL: fun0: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vlr %v0, %v24 +; CHECK-NEXT: br %r14 +entry: + %Res = extractelement <4 x half> %0, i32 0 + ret half %Res +} + +; Test COPY from $f0 to $f24. +define <4 x half> @fun1(half %0) { +; CHECK-LABEL: fun1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: stmg %r14, %r15, 112(%r15) +; CHECK-NEXT: .cfi_offset %r14, -48 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: aghi %r15, -160 +; CHECK-NEXT: .cfi_def_cfa_offset 320 +; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT +; CHECK-NEXT: aebr %f0, %f0 +; CHECK-NEXT: brasl %r14, __truncsfhf2@PLT +; CHECK-NEXT: vlr %v24, %v0 +; CHECK-NEXT: lmg %r14, %r15, 272(%r15) +; CHECK-NEXT: br %r14 +entry: + %Add = fadd half %0, %0 + %Res = insertelement <4 x half> poison, half %Add, i32 0 + ret <4 x half> %Res +} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
